iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	clangformat	gatecat	2023-01-25	1	-1/+1
*	Added fallback to VCC as the preferred constant if the architecture does not ...	Maciej Kurc	2022-05-12	1	-4/+2
*	Added tying unused LUT pins to preferred constant instead of Vcc	Maciej Kurc	2022-05-11	1	-2/+8
*	Generalized representation of unused LUT pins connections	Maciej Kurc	2022-05-11	1	-38/+44
*	Added more code comments, formatted the code	Maciej Kurc	2021-07-22	1	-2/+3
*	LUT mapping ceche optimizations 2	Maciej Kurc	2021-07-16	1	-80/+0
*	Working site LUT mapping cache	Maciej Kurc	2021-07-16	1	-15/+92
*	Using hashlib in arches	gatecat	2021-06-02	1	-7/+7
*	clangformat	gatecat	2021-04-12	1	-7/+4
*	[interchange] Prevent site router from generating incorrect LUTs.	Keith Rothman	2021-04-06	1	-6/+12
*	[interchange] Add crude pseudo pip model.	Keith Rothman	2021-04-06	1	-1/+41
*	Add some FIXME's around VCC assumption in LUT logic.	Keith Rothman	2021-03-25	1	-0/+17
*	Re-work LUT mapping logic to only put VCC pins when required.	Keith Rothman	2021-03-25	1	-5/+111
*	Refactor header structures in FPGA interchange Arch.	Keith Rothman	2021-03-19	1	-1/+17
*	Use NEXTPNR_NAMESPACE macro's now that headers are seperated.	Keith Rothman	2021-03-15	1	-1/+1
*	clangformat	gatecat	2021-03-03	1	-92/+86
*	Initial LUT rotation logic.	Keith Rothman	2021-02-26	1	-0/+370