| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix small isses and code formatting | Maciej Dudek | 2021-09-27 | 1 | -4/+4 |
| * | Change Cluster placement algorithm | Maciej Dudek | 2021-09-23 | 1 | -2/+0 |
| * | Adding MacroCell placement | Maciej Dudek | 2021-09-23 | 1 | -1/+6 |
| * | Adding support for MacroCells | Maciej Dudek | 2021-09-23 | 1 | -0/+1 |
| * | interchange: clusters: fix other cluster allowance checks in same site | Alessandro Comodi | 2021-08-31 | 1 | -7/+2 |
| * | interchange: disallow placing cells on sites with clusters | Alessandro Comodi | 2021-08-27 | 1 | -3/+20 |
| * | Merge pull request #757 from antmicro/lut-mapping-cache | gatecat | 2021-07-22 | 1 | -0/+3 |
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| | * | Added an option to disable the LUT mapping cache | Maciej Kurc | 2021-07-22 | 1 | -1/+2 |
| | * | Working site LUT mapping cache | Maciej Kurc | 2021-07-16 | 1 | -0/+2 |
| * | | interchange: add constraints constraints application routine | Alessandro Comodi | 2021-07-12 | 1 | -0/+3 |
| * | | interchange: reduce run-time to check dedicated interconnect | Alessandro Comodi | 2021-07-08 | 1 | -1/+1 |
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| * | interchange: Allow pseudo pip wires to overlap with bound site wires on the s... | gatecat | 2021-07-06 | 1 | -1/+2 |
| * | interchange: Improve search for PAD-attached bels | gatecat | 2021-07-06 | 1 | -1/+2 |
| * | interchange: Track the macros that cells have been expanded from | gatecat | 2021-06-29 | 1 | -0/+1 |
| * | Fixing old emails and names in copyrights | gatecat | 2021-06-12 | 1 | -2/+2 |
| * | interchange: run clang formatter | Alessandro Comodi | 2021-06-11 | 1 | -1/+1 |
| * | interchange: add support for generating BEL clusters | Alessandro Comodi | 2021-06-11 | 1 | -14/+41 |
| * | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -11/+11 |
| * | interchange: Preliminary implementation of macro expansion | gatecat | 2021-05-21 | 1 | -0/+2 |
| * | interchange: Adding a basic global buffer placer | gatecat | 2021-05-07 | 1 | -0/+2 |
| * | interchange: Initial global routing implementation | gatecat | 2021-05-07 | 1 | -0/+6 |
| * | Add stub cluster API impl for remaining arches | gatecat | 2021-05-06 | 1 | -0/+13 |
| * | interchange: Handle disconnected/missing cell pins | gatecat | 2021-04-19 | 1 | -0/+3 |
| * | clangformat | gatecat | 2021-04-12 | 1 | -3/+3 |
| * | [interchange] Remove requirement to have wire_lut. | Keith Rothman | 2021-04-06 | 1 | -0/+3 |
| * | [interchange] Scale edge cost of pseudo pips. | Keith Rothman | 2021-04-06 | 1 | -5/+1 |
| * | [interchange] Disallow site edges during general routing. | Keith Rothman | 2021-04-06 | 1 | -0/+1 |
| * | [interchange] Add crude pseudo pip model. | Keith Rothman | 2021-04-06 | 1 | -2/+14 |
| * | interchange: Fix illegal placements | gatecat | 2021-03-30 | 1 | -6/+5 |
| * | Implement debugging tools for site router. | Keith Rothman | 2021-03-25 | 1 | -0/+2 |
| * | Re-work LUT mapping logic to only put VCC pins when required. | Keith Rothman | 2021-03-25 | 1 | -1/+0 |
| * | Add initial handling of local site inverters and constant signals. | Keith Rothman | 2021-03-25 | 1 | -0/+13 |
| * | [FPGA interchange] Small fix to get_net_type. | Keith Rothman | 2021-03-25 | 1 | -3/+8 |
| * | Merge pull request #644 from litghost/add_global_buffers | gatecat | 2021-03-23 | 1 | -1/+13 |
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| | * | [FPGA interchange] Add support for global buffers from chipdb. | Keith Rothman | 2021-03-23 | 1 | -1/+13 |
| * | | Merge pull request #643 from litghost/id_constants | gatecat | 2021-03-23 | 1 | -0/+2 |
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| | * | [FPGA interchange] Convert some string constants to IdString. | Keith Rothman | 2021-03-23 | 1 | -0/+2 |
| * | | Initial version of inverter logic. | Keith Rothman | 2021-03-23 | 1 | -0/+6 |
| * | | Use new parameter definition data in FPGA interchange processing. | Keith Rothman | 2021-03-23 | 1 | -0/+2 |
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| * | Initial lookahead for FPGA interchange. | Keith Rothman | 2021-03-23 | 1 | -0/+8 |
| * | Merge pull request #637 from litghost/refine_site_router | gatecat | 2021-03-22 | 1 | -0/+3 |
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| | * | Rework FPGA interchange site router. | Keith Rothman | 2021-03-22 | 1 | -0/+3 |
| * | | Add "checkPipAvailForNet" to Arch API. | Keith Rothman | 2021-03-22 | 1 | -1/+1 |
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| * | Add pseudo pip data to chipdb (with schema bump). | Keith Rothman | 2021-03-22 | 1 | -0/+14 |
| * | Refactor header structures in FPGA interchange Arch. | Keith Rothman | 2021-03-19 | 1 | -876/+160 |
| * | Use NEXTPNR_NAMESPACE macro's now that headers are seperated. | Keith Rothman | 2021-03-15 | 1 | -1/+1 |
| * | Split nextpnr.h to allow for linear inclusion. | Keith Rothman | 2021-03-15 | 1 | -7/+9 |
| * | Initial LUT rotation logic. | Keith Rothman | 2021-02-26 | 1 | -1/+34 |
| * | Fix assorted bugs in FPGA interchange. | Keith Rothman | 2021-02-23 | 1 | -33/+21 |
| * | Working FF example now that constant merging is done. | Keith Rothman | 2021-02-23 | 1 | -1/+3 |
