iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	clangformat	gatecat	2021-02-17	1	-3/+4
*	Require `--package` when arch BBA contains multiple packages.	Keith Rothman	2021-02-16	1	-3/+11
*	[FPGA Interchange] Add Cell -> BEL Pin maps.	Keith Rothman	2021-02-16	1	-7/+161
*	Add FPGA interchange frontend and backend.	Keith Rothman	2021-02-15	1	-2/+19
*	Run "make clangformat".	Keith Rothman	2021-02-12	1	-5/+5
*	Refactor XDC parser into a little class for testing purposes.	Keith Rothman	2021-02-12	1	-0/+11
*	Add FPGA interchange XDC parser.	Keith Rothman	2021-02-12	1	-0/+7
*	interchange: Base on ArchAPI	D. Shah	2021-02-08	1	-3/+1
*	Add RelSlice::ssize and use it when comparing with signed ints.	Keith Rothman	2021-02-05	1	-14/+14
*	Move all string data into BBA file.	Keith Rothman	2021-02-05	1	-8/+8
*	Use RelSlice instead of RelPtr in cases where sizes are present.	Keith Rothman	2021-02-04	1	-17/+17
*	Update APIs to conform to style guide.	Keith Rothman	2021-02-04	1	-10/+10
*	Update copywrite headers.	Keith Rothman	2021-02-04	1	-1/+2
*	Fix warnings with signed/unsigned.	Keith Rothman	2021-02-04	1	-1/+1
*	Run "make clangformat".	Keith Rothman	2021-02-04	1	-36/+23
*	Update FPGA interchange to use IdStringList.	Keith Rothman	2021-02-04	1	-100/+112
*	Start adding data for placement constraint solving.	Keith Rothman	2021-02-04	1	-45/+21
*	Add initial updates to FPGA interchange arch for BEL buckets.	Keith Rothman	2021-02-04	1	-0/+7
*	Address review comments.	Keith Rothman	2021-02-04	1	-8/+5
*	Fix BBA import bugs.	Keith Rothman	2021-02-04	1	-48/+155
*	Assorted fixes to new FPGA interchange based arch.	Keith Rothman	2021-02-04	1	-4/+12
*	Initial compiling version.	Keith Rothman	2021-02-04	1	-0/+9
*	Initial FPGA interchange (which is just a cut-down xilinx arch).	Keith Rothman	2021-02-04	1	-0/+474