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* ecp5: Fix 25k DDRDLLA bitstream genDavid Shah2019-11-292-3/+4
* ecp5: Fix placement of DDRDLLADavid Shah2019-11-291-0/+26
* Merge pull request #356 from YosysHQ/ecp5-ff-densityDavid Shah2019-11-271-0/+153
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| * ecp5: Improve flipflop packing densityDavid Shah2019-11-201-0/+153
* | ECP5 support is no longer experimentalDavid Shah2019-11-264-521/+0
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* Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr"David Shah2019-11-202-74/+5
* ecp5: Add support for promotion of LSRs to global networkDavid Shah2019-11-192-5/+74
* ecp5: Fix handling of custom DEL_VALUEDavid Shah2019-11-181-1/+2
* ecp5: Fix dynamic DELAYF controlDavid Shah2019-11-181-0/+3
* ecp5: Add logic utilisation before packing statisticsDavid Shah2019-11-181-0/+45
* Merge pull request #345 from YosysHQ/dave/sdfDavid Shah2019-11-182-12/+22
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| * ice40: Preserve top level IO properlyDavid Shah2019-10-191-2/+2
| * ecp5: Preserve top level IO properlyDavid Shah2019-10-182-12/+22
* | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
* | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
* | ecp5: Allow setting drive strength for 3V3 IOsDavid Shah2019-10-261-0/+10
* | ecp5: Add constids for new timing cell typesDavid Shah2019-10-262-0/+10
* | ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-264-2/+10
* | ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-253-1/+37
* | ecp5: Make database build depend on constids.incDavid Shah2019-10-201-2/+2
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* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
* ecp5: Fix tristate IO registersDavid Shah2019-10-091-3/+9
* ecp5: Add support for IO registersDavid Shah2019-10-092-0/+103
* ecp5: Add IDDR71B supportDavid Shah2019-10-092-3/+16
* ecp5: Add ODDR71B supportDavid Shah2019-10-091-3/+14
* ecp5: Preparations for new IO belsDavid Shah2019-10-093-1/+16
* ecp5: Fix parametersDavid Shah2019-10-041-0/+4
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-014-19/+96
* Merge pull request #332 from YosysHQ/dave/python-refactorDavid Shah2019-09-191-96/+2
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| * python: Refactor out bindings shared between ECP5 and iCE40David Shah2019-09-151-96/+2
* | Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-p...David Shah2019-09-191-18/+31
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| * | ecp5: add support for PREGENERATED_BBA_PATHSean Cross2019-09-171-18/+31
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* | Merge pull request #330 from zeldin/bbaDavid Shah2019-09-191-5/+6
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| * CMake: Generate chipdbs in build tree when building out-of-treeMarcus Comstedt2019-09-151-3/+4
| * bba: Require explicit endianness flag, and supply itMarcus Comstedt2019-09-151-2/+2
* | python: Fix getWireBelPinsDavid Shah2019-09-152-0/+20
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* Merge pull request #329 from YosysHQ/dave/net_aliasesDavid Shah2019-09-131-0/+5
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| * json: Add support for net aliasesDavid Shah2019-09-131-0/+5
* | ecp5: Move clock constraints across IO and DCCADavid Shah2019-09-131-0/+9
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* ecp5: use $PYTHON_EXECUTABLE for python pathSean Cross2019-09-091-2/+2
* ecp5: Add support for clock gating with DCCADavid Shah2019-08-312-39/+87
* ecp5: Add full part name to bitstream headerDavid Shah2019-08-273-0/+23
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-274-3/+22
* Rename clock restriction attribute to "noglobal"Arnaud Durand2019-08-241-2/+2
* Restrict clock promotion to globalArnaud Durand2019-08-221-0/+3
* Merge pull request #309 from YosysHQ/dsptimingDavid Shah2019-08-092-2/+25
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| * ecp5: Conservative analysis of comb DSP timingDavid Shah2019-07-082-2/+25
* | Add deprecation warning for default packagesDavid Shah2019-08-081-1/+4
* | ecp5: Fix handling of missing ports in LUT permutationDavid Shah2019-08-081-0/+4
* | clangfromatDavid Shah2019-08-071-2/+5
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