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* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-17/+17
* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-6/+7
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-021-1/+1
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-25/+21
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
* ecp5: Fix some tricky ECLKSYNCB/CLKDIVF packing casesDavid Shah2020-10-091-0/+64
* Merge pull request #489 from YosysHQ/dave/ecp5-fix-ioddrx2David Shah2020-08-131-8/+8
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| * ecp5: Fix how ODDRX2 SCLK/RST are setDavid Shah2020-08-131-8/+8
* | ecp5: Run fixupHierarchy after packingDavid Shah2020-08-121-0/+1
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* ecp5: Fix derivation of OSCG timing constraintDavid Shah2020-06-291-1/+5
* ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
* Further condenseRoss Schlaikjer2020-04-291-11/+10
* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-13/+34
* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-0/+35
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-0/+23
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| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-2/+13
| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-0/+10
* | ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pinDavid Shah2020-04-031-0/+10
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* ecp5: Fix tieoff of unused DELAY signalsDavid Shah2020-01-211-3/+3
* ecp5: Add support for flipflops with preloadDavid Shah2019-12-071-2/+6
* ecp5: Fix placement of DDRDLLADavid Shah2019-11-291-0/+26
* ecp5: Improve flipflop packing densityDavid Shah2019-11-201-0/+153
* ecp5: Fix handling of custom DEL_VALUEDavid Shah2019-11-181-1/+2
* ecp5: Add logic utilisation before packing statisticsDavid Shah2019-11-181-0/+45
* Merge pull request #345 from YosysHQ/dave/sdfDavid Shah2019-11-181-11/+3
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| * ecp5: Preserve top level IO properlyDavid Shah2019-10-181-11/+3
* | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
* | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
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* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
* ecp5: Fix tristate IO registersDavid Shah2019-10-091-3/+9
* ecp5: Add support for IO registersDavid Shah2019-10-091-0/+97
* ecp5: Add IDDR71B supportDavid Shah2019-10-091-3/+15
* ecp5: Add ODDR71B supportDavid Shah2019-10-091-3/+14
* ecp5: Fix parametersDavid Shah2019-10-041-0/+4
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-0/+53
* ecp5: Move clock constraints across IO and DCCADavid Shah2019-09-131-0/+9
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-0/+11
* ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-1/+7
* ecp5: Add a check for legacy parameter valuesDavid Shah2019-08-061-0/+12
* ecp5: New Property interfaceDavid Shah2019-08-051-62/+66
* ecp5: Fix missing LUT inputs, fixes #301David Shah2019-07-101-0/+4
* Use flags for each stepMiodrag Milanovic2019-06-141-1/+1
* Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+1
* ecp5: Use an attribute to store is_globalDavid Shah2019-06-071-2/+6
* WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+1
* Added support for attributes/properties typesMiodrag Milanovic2019-06-011-1/+1
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