| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 1 | -1/+14 |
| * | Add more types of wires | Miodrag Milanovic | 2019-10-20 | 1 | -1/+30 |
| * | wd wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+11 |
| * | clk and lsr muxes | Miodrag Milanovic | 2019-10-20 | 1 | -0/+31 |
| * | draw rest of slice wires and more from switchbox | Miodrag Milanovic | 2019-10-20 | 1 | -4/+54 |
| * | Optimize | Miodrag Milanovic | 2019-10-20 | 1 | -6/+83 |
| * | Add other side of slice wires | Miodrag Milanovic | 2019-10-20 | 1 | -5/+94 |
| * | Display rest of slice input wires | Miodrag Milanovic | 2019-10-20 | 1 | -1/+61 |
| * | Start adding visible wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+25 |
| * | Draw swbox, smaller slices, proper io | Miodrag Milanovic | 2019-10-20 | 1 | -5/+22 |
| * | ecp5: Add Bel graphics | David Shah | 2018-07-31 | 1 | -0/+35 |
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index : iCE40/nextpnr | |
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