| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Some refactoring of Chip API (prep for chipdb refactoring) | Clifford Wolf | 2018-06-16 | 1 | -2/+2 |
| * | Refactor position/delay estimation API | Clifford Wolf | 2018-06-14 | 1 | -28/+5 |
| * | Update chip Graphics API | Clifford Wolf | 2018-06-13 | 1 | -4/+4 |
| * | Redesign PosInfo API | Clifford Wolf | 2018-06-13 | 1 | -0/+37 |
| * | Add fast IdString <-> PortPin conversion | Clifford Wolf | 2018-06-12 | 1 | -0/+3 |
| * | Add nextpnr namespace | Clifford Wolf | 2018-06-12 | 1 | -0/+4 |
| * | Add "nextpnr.h" | Clifford Wolf | 2018-06-11 | 1 | -1/+1 |
| * | Remove pool, dict, vector namespace aliases | Clifford Wolf | 2018-06-11 | 1 | -27/+36 |
| * | Add conflicting=false argument to bind getters | Clifford Wolf | 2018-06-11 | 1 | -3/+3 |
| * | Draw fpga model | Miodrag Milanovic | 2018-06-10 | 1 | -0/+24 |
| * | Pass design to gui, display chip name | Miodrag Milanovic | 2018-06-10 | 1 | -0/+1 |
| * | Add dummy implementations of dummy Chip API | Clifford Wolf | 2018-06-09 | 1 | -0/+94 |
| * | Reformat remaining files | David Shah | 2018-06-08 | 1 | -4/+1 |
| * | Fix placer build for dummy arch | Clifford Wolf | 2018-06-07 | 1 | -0/+11 |
| * | clang-format for design and chip codebase | Clifford Wolf | 2018-06-07 | 1 | -3/+1 |
| * | Update and simplify dummy arch | Clifford Wolf | 2018-06-06 | 1 | -10/+0 |
| * | Add Makefile | Clifford Wolf | 2018-05-26 | 1 | -0/+19 |
| * | Directory structure | Clifford Wolf | 2018-05-26 | 1 | -0/+15 |
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index : iCE40/nextpnr | |
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