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| * | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-152-0/+8
|\ \ | | | | | | Add Python bindings for placement tests
| * | Add Python bindings for placement testsgatecat2021-04-152-0/+8
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #680 from YosysHQ/gatecat/fix-utilgatecat2021-04-151-2/+2
|\ \ \ | |/ / |/| | Fix utilisation report when bel buckets are used
| * | Fix utilisation report when bel buckets are usedgatecat2021-04-151-2/+2
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1421-71/+136
|\ \ | | | | | | interchange: add FASM generation target and clean-up tests
| * | gh-actions: increase python-fpga-interchange tag versionAlessandro Comodi2021-04-141-1/+1
| | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
| |/ | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #679 from YosysHQ/gatecat/disable-abslgatecat2021-04-1411-63/+54
|\ \ | |/ |/| Hash table changes
| * ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Hash table refactoringgatecat2021-04-1410-62/+53
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #677 from YosysHQ/gatecat/ppip-no-inputgatecat2021-04-131-14/+35
|\ | | | | interchange: Allow pseudo-cells with no input pins
| * interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
| | | | | | | | | | | | | | These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch, which will probably be required for UltraScale too. Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #676 from YosysHQ/gatecat/fix-sta-crashgatecat2021-04-132-58/+73
|\ \ | |/ |/| timing: Fix domain init when loops are present
| * timing: Fix domain init when loops are presentgatecat2021-04-132-58/+73
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #674 from adamgreig/heap-spreader-fixgatecat2021-04-121-0/+4
|\ | | | | HeAP: Skip high-strength cells in both cell loops
| * HeAP: Skip high-strength cells in both cell loops.Adam Greig2021-04-121-0/+4
| | | | | | | | | | | | Previously only the first loop skipped cells with high belStrength, but they can't be processed by the second loop either, so skip them there too.
* | Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-refgatecat2021-04-121-14/+18
|\ \ | |/ |/| fast_bels: Don't return pointer that might become invalid
| * fast_bels: Don't return pointer that might become invalidgatecat2021-04-121-14/+18
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-04-128-133/+134
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vccgatecat2021-04-091-6/+10
|\ | | | | interchange: Disambiguate cell and bel pins when creating Vcc ties
| * interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #669 from YosysHQ/gatecat/prjoxide-pingatecat2021-04-092-0/+3
|\ \ | |/ |/| interchange: Pin prjoxide commit in CI
| * interchange: Pin prjoxide commitgatecat2021-04-092-0/+3
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #667 from YosysHQ/fix_qtMiodrag Milanović2021-04-081-0/+4
|\ | | | | Add same fix as in issue #373
| * Add same fix as in issue #373Miodrag Milanovic2021-04-081-0/+4
|/
* Merge pull request #665 from cr1901/optional-ltogatecat2021-04-071-2/+13
|\ | | | | Add CMake option to enable IPO (enabled by default).
| * Add CMake option to enable IPO (enabled by default).William D. Jones2021-04-071-2/+13
|/
* Merge pull request #659 from litghost/pseudo_pip_fixesgatecat2021-04-0611-66/+882
|\ | | | | [interchange] Pseudo pip fixes
| * [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Don't fail-fast for GH actions to allow for easier CI debugging.Keith Rothman2021-04-061-0/+3
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
| | | | | | | | | | | | | | | | | | The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-062-5/+12
| | | | | | | | | | | | | | Previous pseudo pips were the same cost as regular pips, but this is definitely too fast, and meant that the router was prefering them. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Fix missing inline methods in site_arch.impl.hKeith Rothman2021-04-062-8/+9
| | | | | | | | | | | | | | getBelPinWire and getBelPinType are marked as always inline, but were not defined in a header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
| | | | | | | | | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #663 from litghost/fix_router2_without_bbgatecat2021-04-061-1/+13
|\| | | | | Fix bug in router2 where router may give up too early.
| * Fix bug in router2 where router may give up too early.Keith Rothman2021-04-061-1/+13
|/ | | | | | | | | | Was introduced in #612. The logic before was intended to prevent the router from terminating early when not using a bounding box, but the fix in #612 simply removed that, meaning that the router might terminate early incorrectly. The solution here is to only use the toexplore hysteric once a solution is found. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #661 from litghost/document_site_routergatecat2021-04-061-10/+58
|\ | | | | [interchange] Add some documentation for the site router.
| * [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #662 from litghost/fix_cirrus_cigatecat2021-04-061-1/+1
|\ \ | | | | | | Increase vCPU to 5 because of cirrus resource limit change.
| * | Increase vCPU to 5 because of cirrus resource limit change.Keith Rothman2021-04-051-1/+1
| |/ | | | | | | | | | | Cirrus CI now requires that RAM (in GiB) be less than 4*vCPU. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #657 from acomodi/interchange-counter-multi-boardgatecat2021-04-065-23/+25
|\ \ | |/ |/| interchange: counter: testing on multiple boards
| * interchange: counter: testing on multiple boardsAlessandro Comodi2021-04-015-23/+25
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #658 from litghost/increment_chipdbgatecat2021-04-025-5/+14
|\ \ | |/ |/| [interchange] Update to v6 of FPGA interchange chipdb.
| * [interchange] Update interchange CI for new chipdb change.Keith Rothman2021-04-012-3/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-013-2/+12
|/ | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 22:35:42 +0000