[interchange] Remove requirement to have wire_lut.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

3 files changed, 7 insertions, 6 deletions

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index f9209922..f1eeae6e 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -285,12 +285,6 @@ Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false)
         }
     }
 
-    // There should be a cell that is a single input LUT.
-    //
-    // Note: This assumption may be not true, revisit if this becomes a
-    // problem.
-    NPNR_ASSERT(wire_lut != nullptr);
-
     raw_bin_constant = std::regex("[01]+", std::regex_constants::ECMAScript | std::regex_constants::optimize);
     verilog_bin_constant =
             std::regex("([0-9]+)'b([01]+)", std::regex_constants::ECMAScript | std::regex_constants::optimize);
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index a6ea70d8..e9c2802a 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -1065,6 +1065,9 @@ struct Arch : ArchAPI<ArchRanges>
     std::unordered_map<IdString, const LutCellPOD *> lut_cells;
 
     // Of the LUT cells, which is used for wires?
+    // Note: May be null in arch's without wire LUT types.  Assumption is
+    // that these arch's don't need wire LUT's because the LUT share is simple
+    // enough to avoid it.
     const LutCellPOD * wire_lut;
 
     std::regex raw_bin_constant;
diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc
index c34e3de7..58b4a69b 100644
--- a/fpga_interchange/pseudo_pip_model.cc
+++ b/fpga_interchange/pseudo_pip_model.cc
@@ -363,6 +363,10 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) {
         cell.bel.tile = tile;
         cell.bel.index = bel_pair.first;
 
+        if(ctx->wire_lut == nullptr) {
+            continue;
+        }
+
         cell.type = IdString(ctx->wire_lut->cell);
         NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
         cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));