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* | Merge pull request #948 from antmicro/dcs_supportgatecat2022-03-165-4/+58
|\ \ | | | | | | nexus: DCS support
| * | nexus: Corrected auto frequency constraint for LF output of OSCAMaciej Kurc2022-03-161-2/+2
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | nexus: Added support for the DCS BelMaciej Kurc2022-03-165-3/+57
|/ / | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #949 from yrabbit/thousandsgatecat2022-03-161-1/+8
|\ \ | |/ |/| BUGFIX: disable the thousands separator
| * BUGFIX: disable the thousands separatorYRabbit2022-03-161-1/+8
|/ | | | | | | The wire numbers are very large and it is undesirable to use a thousand separator there. This is a side effect of enabling locale. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #943 from yrabbit/localegatecat2022-03-152-1/+10
|\ | | | | gowin: support for locales other than en_US and C
| * Set the locale as early as possibleYRabbit2022-03-162-10/+9
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: test locale workaroundYRabbit2022-03-151-1/+5
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: support for locales other than en_US and CYRabbit2022-03-141-0/+6
| | | | | | | | | | | | | | Specifically, those locales where the fractional part separator in floating point numbers is not a dot. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #944 from Riesi/mastergatecat2022-03-151-24/+27
|\ \ | | | | | | ice40: fix crash when packing LUTs with no output
| * | ice40: fix crash when packing LUTs with no outputStefan Riesenberger2022-03-141-24/+27
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* | | Merge pull request #947 from antmicro/dcc_enhancementsgatecat2022-03-152-0/+20
|\ \ \ | | | | | | | | nexus: DCC support fixups
| * | | nexus: Added FASM feature emission for DCC and port timing class infoMaciej Kurc2022-03-152-0/+20
|/ / / | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Merge pull request #945 from yrabbit/wip-oddrgatecat2022-03-155-11/+177
|\ \ \ | |/ / |/| | gowin: add support for ODDR primitive
| * | gowin: add support for ODDR primitiveYRabbit2022-03-155-11/+177
|/ / | | | | | | | | | | | | | | | | Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #942 from yrabbit/bugfix-1gatecat2022-03-141-0/+5
|\ \ | |/ |/| gowin: BUGFIX temporarily disable the budget
| * fix identationYRabbit2022-03-141-4/+4
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: BUGFIX temporarily disable the budgetYRabbit2022-03-141-0/+5
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #938 from Ravenslofty/mistral-m10kinitgatecat2022-03-122-2/+18
|\ | | | | mistral: M10K initialisation support
| * mistral: M10K initialisation supportLofty2022-03-122-2/+18
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* | Merge pull request #940 from VioletEternity/truncated-config-wordsgatecat2022-03-121-2/+7
|\ \ | | | | | | ecp5: accept lowercase characters in hex strings
| * | ecp5: accept lowercase characters in hex strings.Maya2022-03-111-1/+1
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| * | ecp5: verify hex strings contain only valid characters.Maya2022-03-111-1/+6
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* | | Merge pull request #941 from yrabbit/gsrgatecat2022-03-124-0/+51
|\ \ \ | |/ / |/| | gowin: Add the Global Set/Reset primitive
| * | gowin: Add the Global Set/Reset primitiveYRabbit2022-03-124-0/+51
|/ / | | | | | | | | | | | | | | | | GSR is added automatically if it was not instantiated by the user explicitly. Compatible with old apicula bases, the functionality does not work, but the crash does not happen --- just a warning. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #939 from antmicro/fix-global-routergatecat2022-03-111-1/+1
|\ \ | | | | | | [fpga_interchange] FIX: Don't hold reference to current visit in route_global_arc
| * | interchange: Don't hold reference to visit in global routingKrzysztof Boronski2022-03-111-1/+1
|/ / | | | | | | Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
* | Merge pull request #886 from Ravenslofty/mistral-m10kgatecat2022-03-097-0/+233
|\| | | | | mistral: M10K support
| * mistral: fixes and debug infoLofty2022-03-094-29/+59
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| * mistral: some more M10K fixesLofty2022-03-092-7/+5
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| * mistral: M10K pack fixesgatecat2022-03-092-6/+14
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: preliminary bitstream infoLofty2022-03-091-0/+41
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| * mistral: move M10K code to packLofty2022-03-092-71/+77
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| * mistral: M10K cell functionLofty2022-03-092-2/+75
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| * mistral: add M10K belLofty2022-03-094-1/+78
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* clangformatgatecat2022-03-094-10/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #937 from antmicro/mdudek/nexus_implicit_DCC_cascadinggatecat2022-03-091-1/+1
|\ | | | | nexus: DCCs cannot be cascaded
| * nexus: DCCs cannot be cascadedMaciej Dudek2022-03-091-1/+1
| | | | | | | | | | | | This commit solves implicit cascading when clock signal drives DCC and logic Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #936 from whitequark/wasm-no-parallel-refinegatecat2022-03-081-1/+4
|\ \ | |/ |/| Add missing part of PR #933
| * Add missing part of commit aee35768.Catherine2022-03-081-1/+4
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* | Merge pull request #933 from whitequark/wasm-no-parallel-refinegatecat2022-03-052-1/+19
|\| | | | | Disable parallel refinement on WebAssembly
| * Disable parallel refinement on WebAssembly.Catherine2022-03-052-1/+19
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* Merge pull request #932 from ↵gatecat2022-03-044-12/+21
|\ | | | | | | | | antmicro/remove-hardcoded-values-from-lut-mapping-cache interchange: lut map cache: remove hardcoded values
| * interchange: lut map cache: remove hardcoded valuesAlessandro Comodi2022-03-044-12/+21
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #931 from yrabbit/bugfix-0gatecat2022-03-041-0/+10
|\ \ | |/ |/| gowin: BUGFIX gui crash
| * gowin: BUGFIX gui crashYRabbit2022-03-041-0/+10
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #929 from gatecat/gatecat/parallel_refinegatecat2022-03-035-2/+1012
|\ \ | | | | | | parallel_refine: New, parallelised placement refinement pass
| * | parallel_refine: New, parallelised placement refinement passgatecat2022-03-035-2/+1012
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* | Merge pull request #925 from YosysHQ/gatecat/netlist-ivgatecat2022-03-0134-457/+701
|\ \ | | | | | | Switch to potentially-sparse net users array
| * | Switch to potentially-sparse net users arraygatecat2022-02-2734-465/+442
| | | | | | | | | | | | | | | | | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
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