mistral: fixes and debug info

4 files changed, 59 insertions, 29 deletions

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 660e3671..6a2c3825 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -118,7 +118,7 @@ struct MistralBitgen
         cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
     }
 
-    void write_m10k_cell(CellInfo* ci, int x, int y, int bi)
+    void write_m10k_cell(CellInfo *ci, int x, int y, int bi)
     {
         auto pos = CycloneV::xy2pos(x, y);
 
@@ -128,31 +128,32 @@ struct MistralBitgen
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
         cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
-        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::ASYNC);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SAEN_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WL_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
 
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
         cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
-        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::ASYNC);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SAEN_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WL_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WR_TIMER_PULSE, bi, 0x0b);
 
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
 
-        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 0);
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0);
 
+        // Note for future us: the RAM init contents are inverted.
         for (int bi = 0; bi < 256; bi++)
             cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff);
     }
diff --git a/mistral/constids.inc b/mistral/constids.inc
index e032bf53..262fd12a 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -90,6 +90,7 @@ X(WE)
 X(MISTRAL_MLAB)
 X(CLK1)
 X(A1EN)
+X(B1EN)
 X(A1DATA)
 X(B1DATA)
 X(WCLK_INV)
diff --git a/mistral/delay.cc b/mistral/delay.cc
index 4d123249..c40ac3f0 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -57,6 +57,17 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         } else if (port.in(id_B1DATA)) {
             return TMG_COMB_OUTPUT;
         }
+    } else if (cell->type == id_MISTRAL_M10K) {
+        if (port == id_CLK1) {
+            return TMG_CLOCK_INPUT;
+        } else if (port.in(id_A1DATA, id_A1EN, id_B1EN) || port.str(this).find("A1ADDR") == 0) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        } else if (port.str(this).find("B1ADDR") == 0) {
+            return TMG_REGISTER_INPUT;
+        } else if (port.in(id_B1DATA)) {
+            return TMG_REGISTER_OUTPUT;
+        }
     }
     return TMG_IGNORE;
 }
@@ -87,6 +98,31 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             timing.clockToQ = DelayQuad{};
         }
         return timing;
+    } else if (cell->type == id_MISTRAL_M10K) {
+        timing.clock_port = id_CLK1;
+        timing.edge = RISING_EDGE;
+        if (port.str(this).find("A1ADDR") == 0 || port.str(this).find("B1ADDR") == 0) {
+            timing.setup = DelayPair{125, 125};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_A1DATA) {
+            timing.setup = DelayPair{97, 97};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_A1EN) {
+            timing.setup = DelayPair{140, 140};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_B1EN) {
+            timing.setup = DelayPair{161, 161};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_B1DATA) {
+            timing.setup = DelayPair{};
+            timing.hold = DelayPair{};
+            timing.clockToQ = DelayQuad{1004};
+        }
+        return timing;
     }
     NPNR_ASSERT_FALSE("unreachable");
 }
diff --git a/mistral/m10k.cc b/mistral/m10k.cc
index 6d51625e..4da1204f 100644
--- a/mistral/m10k.cc
+++ b/mistral/m10k.cc
@@ -24,35 +24,27 @@ NEXTPNR_NAMESPACE_BEGIN
 void Arch::create_m10k(int x, int y)
 {
     BelId bel = add_bel(x, y, id_MISTRAL_M10K, id_MISTRAL_M10K);
-    add_bel_pin(bel, id_ADDRSTALLA, PORT_IN,
-                get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
-    add_bel_pin(bel, id_ADDRSTALLB, PORT_IN,
-                get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
+    add_bel_pin(bel, id_ADDRSTALLA, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
+    add_bel_pin(bel, id_ADDRSTALLB, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
     for (int z = 0; z < 2; z++) {
         add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
         add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
-        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
-        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
-        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z+6)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z+6));
+        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
+        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
+        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
+        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
+        add_bel_pin(bel, id(stringf("CLKIN[%d]", z + 6)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6));
     }
     for (int z = 0; z < 4; z++) {
         add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
     }
     for (int z = 0; z < 12; z++) {
-        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
-        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
+        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
+        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
     }
     for (int z = 0; z < 20; z++) {
         add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
@@ -66,4 +58,4 @@ void Arch::create_m10k(int x, int y)
     }
 }
 
-NEXTPNR_NAMESPACE_END
\ No newline at end of file
+NEXTPNR_NAMESPACE_END