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* | timing: Model clock to Q timesDavid Shah2018-07-242-0/+18
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Trim BRAM constant inputs, reduces routing congestion around BRAMDavid Shah2018-07-241-0/+3
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: fixes before reviewSergiusz Bazanski2018-07-246-47/+14
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| * ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-243-69/+40
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| * ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-244-16/+22
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| * clang-formatSergiusz Bazanski2018-07-244-67/+74
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| * ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
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| * ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-243-56/+53
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| * ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
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| * ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-244-74/+59
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| * ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-243-5/+159
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| * ice40: Fail early on SB_PLL40_*_PAD cellsSergiusz Bazanski2018-07-242-0/+14
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| * ice40: Implement emitting PLLsSergiusz Bazanski2018-07-2412-17/+275
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* make update of tree for nets and cells partialMiodrag Milanovic2018-07-232-26/+56
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* ecp5: Add some more PIO helper functionsDavid Shah2018-07-232-0/+42
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Helper functions for I/O placement and checkingDavid Shah2018-07-233-0/+324
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Proper highlight/selected cleanup on context re-initMiodrag Milanovic2018-07-232-0/+4
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* write frequency infoMiodrag Milanovic2018-07-231-0/+1
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* always assign budget before placingMiodrag Milanovic2018-07-231-2/+2
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* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-235-45/+208
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove getBelsByType() APIClifford Wolf2018-07-234-40/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatDavid Shah2018-07-232-4/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add Add getGridDimX(), getGridDimY(), getTileDimZ()David Shah2018-07-231-0/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatClifford Wolf2018-07-232-20/+26
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add fallback to estimateDelay() in getNetinfoRouteDelay()Clifford Wolf2018-07-231-1/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add getGridDimX(), getGridDimY(), getTileDimZ() APIClifford Wolf2018-07-233-1/+31
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Implement new Grid APIsDavid Shah2018-07-232-0/+50
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Remove obsolete db entries, add Bel z-positionDavid Shah2018-07-232-19/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added Bel port info to GUIMiodrag Milanovic2018-07-221-0/+8
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* Move to new API and remove deprecatedMiodrag Milanovic2018-07-226-94/+40
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* Move to new apiMiodrag Milanovic2018-07-221-12/+3
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* ecp5: Adding new Bel pin APIDavid Shah2018-07-223-3/+63
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix regression following router updateDavid Shah2018-07-222-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add Arch::getBelPins() to generic and iCE40 archsClifford Wolf2018-07-224-0/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-223-4/+57
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Arch::getBelPinType() and Arch::getWireBelPins() in generic archClifford Wolf2018-07-222-2/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-2212-26/+26
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move common patterns from router1 to Context APIClifford Wolf2018-07-223-150/+124
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatClifford Wolf2018-07-225-39/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* QTimer::start(std::chrono::duration -> int)Sergiusz Bazanski2018-07-212-3/+3
| | | | The chrono::duration-friendly method is availble from Qt 5.8 only.
* Merge branch 'q3k/lock-2-electric-boogaloo' into 'master'Clifford Wolf2018-07-217-161/+397
|\ | | | | | | | | Basic locking and threading for Arch/GUI See merge request SymbioticEDA/nextpnr!10
| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Sergiusz Bazanski2018-07-2122-682/+1466
| |\ | | | | | | | | | q3k/lock-2-electric-boogaloo
| * | Re-enable drawing Pips.Sergiusz Bazanski2018-07-201-3/+3
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| * | Use UI lock for yieldingSergiusz Bazanski2018-07-204-14/+40
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| * | clang-formatSergiusz Bazanski2018-07-201-1/+1
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| * | Nuke IdStringDBSergiusz Bazanski2018-07-205-50/+41
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| * | Remove dead code.Sergiusz Bazanski2018-07-201-2/+0
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| * | clang-format and uncomment debugSergiusz Bazanski2018-07-204-45/+39
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