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| author | Sergiusz Bazanski <q3k@q3k.org> | 2018-07-23 16:58:11 +0100 |
|---|---|---|
| committer | Sergiusz Bazanski <q3k@q3k.org> | 2018-07-24 02:55:38 +0100 |
| commit | db31c0625bb722dd9c42fead97d3988659656648 (patch) | |
| tree | df7eb1be9ab90728c61010a40d7c73dfe9ee4089 | |
| parent | 2b1f7875bb8c3a761dfb9db21706f918b58be9c3 (diff) | |
| download | nextpnr-db31c0625bb722dd9c42fead97d3988659656648.tar.gz nextpnr-db31c0625bb722dd9c42fead97d3988659656648.tar.bz2 nextpnr-db31c0625bb722dd9c42fead97d3988659656648.zip | |
ice40: Fail early on SB_PLL40_*_PAD cells
| -rw-r--r-- | ice40/cells.h | 7 | ||||
| -rw-r--r-- | ice40/pack.cc | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/ice40/cells.h b/ice40/cells.h index 404f401c..4bc50e8a 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -78,6 +78,13 @@ inline bool is_sb_pll40(const BaseCtx *ctx, const CellInfo *cell) cell->type == ctx->id("SB_PLL40_2F_CORE"); } +inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell) +{ + return cell->type == ctx->id("SB_PLL40_PAD") || cell->type == ctx->id("SB_PLL40_2_PAD") || + cell->type == ctx->id("SB_PLL40_2F_PAD"); +} + + uint8_t sb_pll40_type(const BaseCtx *ctx, const CellInfo *cell); // Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports diff --git a/ice40/pack.cc b/ice40/pack.cc index f63e14f6..c4d47bf4 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -595,6 +595,13 @@ static void pack_special(Context *ctx) std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL"); packed_cells.insert(ci->name); + + if (is_sb_pll40_pad(ctx, ci)) { + // TODO(q3k): Implement these after checking their behaviour on + // a board with exposed 'clock pads'. + log_error("SB_PLL40_*_PAD cells are not supported yet.\n"); + } + for (auto attr : ci->attrs) packed->attrs[attr.first] = attr.second; for (auto param : ci->params) |