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* Merge pull request #730 from YosysHQ/gatecat/dcc-routehtrugatecat2021-06-173-3/+62
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| * nexus: Disable center DCC-thrus on 17k devicegatecat2021-06-163-1/+29
| * nexus: Fix FASM gen for DCC-thrugatecat2021-06-161-3/+34
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* Merge pull request #728 from YosysHQ/gatecat/nexus-ramgatecat2021-06-157-2/+384
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| * interchange: Bump versionsgatecat2021-06-151-2/+2
| * nexus: Add modified version of RAM testgatecat2021-06-155-0/+206
| * nexus: Add PDPSC16K->PDPSC16K_MODE to remap rulesgatecat2021-06-151-0/+176
* | Merge pull request #729 from acomodi/interchange-fix-phys-net-writergatecat2021-06-151-5/+2
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| * | interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
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* | Merge pull request #727 from YosysHQ/gatecat/ic-undrivengatecat2021-06-143-5/+9
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| * interchange: Cope with undriven nets in more placesgatecat2021-06-143-5/+9
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* Merge pull request #724 from YosysHQ/gatecat/update-namesgatecat2021-06-12204-282/+282
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| * Bump tests submodulegatecat2021-06-121-0/+0
| * Update URLsgatecat2021-06-123-9/+9
| * Fixing old emails and names in copyrightsgatecat2021-06-12201-273/+273
* | Merge pull request #726 from YosysHQ/gatecat/mem-errorsgatecat2021-06-121-1/+1
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| * HeAP: Fix memory error introduced by switch to dictgatecat2021-06-121-1/+1
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* Merge pull request #720 from acomodi/interchange-clustersgatecat2021-06-1113-30/+715
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| * interchange: ci: add RW patch for missing cell bel mapsAlessandro Comodi2021-06-111-0/+3
| * interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
| * interchange: ci: update python-interchange tagAlessandro Comodi2021-06-111-1/+1
| * interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
| * interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
| * interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
| * interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
| * interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
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* Merge branch 'test_framework'gatecat2021-06-112-0/+3
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| * fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
| * tests: fpga_interchange: Update module to use site router test frameworkTomasz Michalak2021-06-111-0/+0
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* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
* nexus: Fix LRAM x coordgatecat2021-06-101-0/+2
* Merge pull request #723 from YosysHQ/gatecat/fix-722gatecat2021-06-083-11/+16
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| * gui: Don't destroy context when loading JSONgatecat2021-06-073-11/+16
* | ecp5: Don't attempt to promote undriven nets to globalsgatecat2021-06-071-1/+2
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* mistral: Fix include path in GUI cmake, toogatecat2021-06-071-1/+1
* Merge pull request #721 from YosysHQ/gatecat/mistral-cmakegatecat2021-06-057-17/+7
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| * ci: Bump mistral versiongatecat2021-06-052-6/+2
| * mistral: Remove mistral root argumentgatecat2021-06-043-7/+1
| * mistral: Build libmistral as a cmake subdirgatecat2021-06-042-4/+4
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* Merge pull request #718 from YosysHQ/gatecat/hashlibgatecat2021-06-03137-1658/+2152
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| * Remove redundant code after hashlib movegatecat2021-06-0220-498/+14
| * Use hashlib in frontend, where possiblegatecat2021-06-021-6/+6
| * Use hashlib in most remaining codegatecat2021-06-0220-58/+53
| * Using hashlib in timinggatecat2021-06-022-82/+26
| * Using hashlib in archesgatecat2021-06-0266-549/+358
| * Use hashlib in routersgatecat2021-06-024-41/+37
| * Bump tests submodulegatecat2021-06-021-0/+0
| * Use hashlib in placersgatecat2021-06-027-52/+43
| * Use hashlib for core netlist structuresgatecat2021-06-0249-368/+383
| * Add hash() member functionsgatecat2021-06-029-7/+51
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