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authorAlessandro Comodi <acomodi@antmicro.com>2021-06-10 12:41:47 +0200
committerAlessandro Comodi <acomodi@antmicro.com>2021-06-11 11:19:01 +0200
commit490ca794c5a934c1a6aeaf681818a6c6d0c4e5e2 (patch)
treec06949ca35672b67917bbfbf27913349a92f7af1
parent104536b7aae5970ae1d1e95394f26fbf04603d12 (diff)
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interchange: tests: counter: emit carries for xc7
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
-rw-r--r--fpga_interchange/examples/tests/counter/counter.v8
-rw-r--r--fpga_interchange/examples/tests/counter/run_xilinx.tcl2
2 files changed, 6 insertions, 4 deletions
diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v
index 00f52a20..4b3f343b 100644
--- a/fpga_interchange/examples/tests/counter/counter.v
+++ b/fpga_interchange/examples/tests/counter/counter.v
@@ -1,13 +1,15 @@
module top(input clk, input rst, output [7:4] io_led);
-reg [31:0] counter = 32'b0;
+localparam SIZE = 32;
-assign io_led = counter >> 22;
+reg [SIZE-1:0] counter = SIZE'b0;
+
+assign io_led = {counter[SIZE-1], counter[25:23]};
always @(posedge clk)
begin
if(rst)
- counter <= 32'b0;
+ counter <= SIZE'b0;
else
counter <= counter + 1;
end
diff --git a/fpga_interchange/examples/tests/counter/run_xilinx.tcl b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
index ffea3b2e..c02cf933 100644
--- a/fpga_interchange/examples/tests/counter/run_xilinx.tcl
+++ b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
@@ -2,7 +2,7 @@ yosys -import
read_verilog $::env(SOURCES)
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+synth_xilinx -nolutram -nowidelut -nosrl -nodsp
techmap -map $::env(TECHMAP)
# opt_expr -undriven makes sure all nets are driven, if only by the $undef