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* Merge pull request #1077 from yrabbit/gw1nsr-4c_0myrtle2023-01-197-38/+209
|\ | | | | gowin: add a PLL primitive for the GW1NS-4 series
| * gowin: improve error messageYRabbit2023-01-191-1/+2
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: to use the FB network detection functionYRabbit2023-01-191-0/+6
| | | | | | | | | | | | | | The chip used in tangnano4k does not have such pins, but we call the function anyway in the expectation of other chips. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-187-38/+202
| | | | | | | | | | | | | | | | | | | | * both instances of the new PLLVR type are supported; * primitive placement is optimized for the use of dedicated PLL clock pins; * all 4 outputs of each primitive can use the clock nets (only 5 lines in total at the same time so far). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1078 from YosysHQ/gatecat/route-delay-quadmyrtle2023-01-183-1/+49
|\ \ | |/ |/| context: Add getNetinfoRouteDelayQuad
| * context: Add getNetinfoRouteDelayQuadgatecat2023-01-183-1/+49
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1076 from adamgreig/ecp5-dsp-remapmyrtle2023-01-044-1/+281
|\ | | | | ECP5: Add DSP signal remapping
| * Add remapping of DSP clk/ce/rst signals in a block.Adam Greig2023-01-044-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each DSP block contains two slices, and each slice contains multiple MULT18X18D and ALU54B units. Each unit configures each register to use any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are connected per unit (so for example, two MULTs in the same block could connect their CLK0s to different external signals). However, the hardware only has one actual port per block, so it's required that all CLK0 signals within a block are the same. Because the packer is in general allowed to combine two unrelated units into one block, it may end up combining units that use different signals for the same port, which would eventually have caused a router failure. This commit adds validity checks which ensure only unique signals are used per block, and adds remapping so that conflicting signals are automatically reassigned when possible and required.
| * Include ALU54B in cell types with wire location overridesAdam Greig2023-01-041-1/+1
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* clangformatgatecat2023-01-022-4/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1075 from YosysHQ/gatecat/ecp5-lpf-errorsmyrtle2023-01-021-9/+10
|\ | | | | ecp5: Improve error handling for missing end-"
| * ecp5: Improve error handling for missing end-"gatecat2023-01-021-9/+10
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1073 from yrabbit/docmyrtle2023-01-011-3/+3
|\ | | | | doc: fix the list format
| * doc: fix the list formatYRabbit2023-01-011-3/+3
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1071 from yrabbit/to-floatmyrtle2022-12-305-50/+85
|\ | | | | gowin: bugfix and improved clock router
| * gowin: improve clock wire routingYRabbit2022-12-305-45/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: correct the delay calculationYRabbit2022-12-291-5/+16
|/ | | | | | | And do a full enumeration when searching for a delay because it is not yet clear whether the orderliness of the vector is guaranteed. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1069 from yrabbit/mistypemyrtle2022-12-271-2/+1
|\ | | | | doc: fix a mistype
| * doc: fix a mistypeYRabbit2022-12-231-2/+1
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1068 from YosysHQ/cleanup_and_syncmyrtle2022-12-226-30/+14
|\ | | | | Cleanup and sync
| * initialize netShareWeightMiodrag Milanovic2022-12-221-0/+1
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| * propagate netShareWeightMiodrag Milanovic2022-12-222-1/+6
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| * Remove deprecated functionsMiodrag Milanovic2022-12-224-29/+7
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* Merge pull request #1066 from arjenroodselaar/place_timeoutmyrtle2022-12-213-6/+26
|\ | | | | Timeout when legal placement can't be found for cell
| * Set divisor instead of absolute valueArjen Roodselaar2022-12-202-5/+10
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| * Allow setting cell placement timeoutArjen Roodselaar2022-12-203-13/+16
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| * Add --no-placer-timeout flag to override timeout during refinementArjen Roodselaar2022-12-193-5/+12
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| * Increase timeoutArjen Roodselaar2022-12-191-2/+4
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| * Timeout when legal placement can't be found for cellArjen Roodselaar2022-12-171-3/+6
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* | Merge pull request #1067 from yrabbit/wasmmyrtle2022-12-213-0/+12
|\ \ | | | | | | gowin: fix build for wasm
| * | gowin: fix build for wasmYRabbit2022-12-213-0/+12
|/ / | | | | | | | | | | | | | | A large number of global variables are not suitable for WASM, so completely disable the graphics part where the main array of them is used. For other architectures GUI is still possible. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1065 from YosysHQ/gatecat/heap-chains-fixmyrtle2022-12-191-2/+2
|\ \ | |/ |/| heap: encourage more spreading of heterogenous chains
| * heap: encourage more spreading of heterogenous chainsgatecat2022-12-171-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1064 from YosysHQ/gatecat/ecp5-main-fixmyrtle2022-12-171-5/+4
|\ \ | | | | | | ecp5: Only write bitstream if --textcfg passed
| * | ecp5: Only write bitstream if --textcfg passedgatecat2022-12-171-5/+4
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1061 from yrabbit/fix-clock-guimyrtle2022-12-141-1/+1
|\ \ | | | | | | gowin: not crush on unknown clock tap's sources
| * | gowin: not crush on unknown clock tap's sourcesYRabbit2022-12-141-1/+1
|/ / | | | | | | | | | | As preparation for possible changes to the clock wiring system. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1060 from yrabbit/pll-inputsmyrtle2022-12-092-13/+14
|\ \ | |/ |/| gowin: BUGFIX: Correctly handle resets
| * gowin: BUGFIX: Correctly handle resetsYRabbit2022-12-092-13/+14
|/ | | | | | | | | | When a single primitive occupies several cells, care must be taken when manipulating the parameters of that primitive: when creating cells, each cell must receive a copy of all the parameters and not modify them unnecessarily. That is, if possible, it is better to make all parameter changes before dividing the primitive into cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-0726-34/+59
|\ | | | | Add new option for verbose validity errors, use for ice40
| * ice40: Add debugs to isBelLocationValid for SB_IOSean Anderson2022-12-071-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there is a constraint conflict while placing IOs, the user gets an error message such as ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO' While this identifies the problematic cell, it does not explain why there is a problem. Add some verbose messages to allow users to determine where the problem is. This can result in something like Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin' which provides something actionable. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-0726-30/+37
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-0727-63/+57
|\| | | | | refactor: rename ArcBounds -> BoundingBox and use this in HeAP
| * heap: Remove custom bounding-box typegatecat2022-12-071-6/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-0726-57/+57
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1055 from yrabbit/pll-pinsmyrtle2022-12-065-16/+140
|\ \ | |/ |/| gowin: add PLL pins processing
| * gowin: change the way networks are handledYRabbit2022-12-061-7/+8
| | | | | | | | | | | | | | Until a comprehensive clock router is developed, the order in which private cases are handled is important. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into pll-pinsYRabbit2022-12-0413-17/+17
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| * | gowin: add PLL pins processingYRabbit2022-12-045-10/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uses the information of the special input pins for the PLL in the current chip. If such pins are involved, no routing is performed and information about the use of implicit wires is passed to the packer. The RESET and RESET_P inputs are now also disabled if they are connected to VSS/VCC. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | Merge pull request #1056 from YosysHQ/gatecat/generic-fix-constsmyrtle2022-12-061-0/+3
|\ \ \ | |_|/ |/| | viaduct: Fix constant connectivity
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