ice40: Add debugs to isBelLocationValid for SB_IO

When there is a constraint conflict while placing IOs, the user gets an
error message such as

ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO'

While this identifies the problematic cell, it does not explain why
there is a problem. Add some verbose messages to allow users to
determine where the problem is. This can result in something like

Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin'

which provides something actionable.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

1 files changed, 22 insertions, 4 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index d8232571..1d69d62f 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -124,6 +124,8 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
                         return true;
 
                     // Conflict
+                    if (explain_invalid)
+                        log_nonfatal_error("Cell '%s' conflicts with PLL cell '%s'\n", nameOf(cell), nameOf(pll_cell));
                     return false;
                 }
             }
@@ -135,18 +137,29 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
             // Check LVDS pairing
             if (cell->ioInfo.lvds) {
                 // Check correct z and complement location is free
-                if (ioLoc.z != 0)
+                if (ioLoc.z != 0) {
+                    if (explain_invalid)
+                        log_nonfatal_error("Bel '%s' can't be used for LVDS\n", getCtx()->nameOfBel(bel));
                     return false;
+                }
                 BelId compBel = getBelByLocation(compLoc);
                 CellInfo *compCell = getBoundBelCell(compBel);
-                if (compCell)
+                if (compCell) {
+                    if (explain_invalid)
+                        log_nonfatal_error("Cell '%s' LVDS complement occupied by cell '%s'\n", nameOf(cell),
+                                           nameOf(compCell));
                     return false;
+                }
             } else {
                 // Check LVDS IO is not placed at complement location
                 BelId compBel = getBelByLocation(compLoc);
                 const CellInfo *compCell = getBoundBelCell(compBel);
-                if (compCell && compCell->ioInfo.lvds)
+                if (compCell && compCell->ioInfo.lvds) {
+                    if (explain_invalid)
+                        log_nonfatal_error("Cell '%s' can't occupy LVDS complement of cell '%s'\n", nameOf(cell),
+                                           nameOf(compCell));
                     return false;
+                }
 
                 // Check for conflicts on shared nets
                 // - CLOCK_ENABLE
@@ -168,8 +181,13 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
                     };
 
                     for (int i = 0; i < 6; i++)
-                        if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr)))
+                        if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) {
+                            if (explain_invalid)
+                                log_nonfatal_error("Net '%s' for cell '%s' conflicts with net '%s' for '%s'\n",
+                                                   nameOf(nets[i]), nameOf(cell), nameOf(nets[i ^ 1]),
+                                                   nameOf(compCell));
                             return false;
+                        }
                 }
             }