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* Merge pull request #761 from acomodi/interchange-constrsgatecat2021-07-125-13/+174
|\ | | | | interchange: add user placement constraints handling
| * interchange: xdc and place constr: address review commentsAlessandro Comodi2021-07-123-23/+13
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: xdc: add get_cells commandAlessandro Comodi2021-07-121-13/+70
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: add constraints constraints application routineAlessandro Comodi2021-07-124-0/+114
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #760 from YosysHQ/gatecat/xcup-ibufdsgatecat2021-07-122-5/+16
|\ | | | | interchange: Support for UltraScale+ differential input buffers
| * interchange: Skip IO ports in dedicated routing checkgatecat2021-07-121-0/+8
| | | | | | | | | | | | These have already been dealt with in arch_pack_io Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Debug IO port validity check failuresgatecat2021-07-122-3/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDSgatecat2021-07-121-3/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #759 from pepijndevos/gw1ndbgatecat2021-07-111-1/+8
|\ | | | | GW1NR is not a seperate family, but GW1NS is
| * GW1NR is not a seperate family, but GW1NS isPepijn de Vos2021-07-111-1/+8
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* Merge pull request #758 from YosysHQ/gatecat/hist-oobgatecat2021-07-111-1/+6
|\ | | | | timing: Fix out-of-bounds histogram bins in all cases
| * timing: Fix out-of-bounds histogram bins in all casesgatecat2021-07-101-1/+6
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge branch 'master' of github.com:YosysHQ/nextpnrgatecat2021-07-106-23/+93
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| * Merge pull request #755 from yrabbit/io_portgatecat2021-07-081-16/+24
| |\ | | | | | | Pin modes parser
| | * Fix the boolean.YRabbit2021-07-081-1/+1
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * Fix formatingYRabbit2021-07-071-24/+24
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * Fix boolean value.YRabbit2021-07-071-1/+1
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * Merge branch 'master' into io_portYRabbit2021-07-0718-78/+201
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| | * | Wip parserYRabbit2021-07-071-16/+4
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | ParserYRabbit2021-07-051-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | Merge branch 'master' into io_portYRabbit2021-07-031-2/+13
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| | * | | Fix parser. Comments and IO_PORTYRabbit2021-07-031-11/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | | SyntaxYRabbit2021-07-021-3/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | | Add IO_PORT parsingYRabbit2021-07-021-14/+27
| | | | | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | | | Merge pull request #756 from acomodi/fix-clustering-runtimegatecat2021-07-085-7/+69
| |\ \ \ \ | | | | | | | | | | | | interchange: reduce run-time to check dedicated interconnect
| | * | | | interchange: bump python-interchange versionAlessandro Comodi2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| | * | | | interchange: update chipdb versionAlessandro Comodi2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| | * | | | interchange: reduce run-time to check dedicated interconnectAlessandro Comodi2021-07-084-5/+67
| |/ / / / | | | | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* / / / / ice40: Fix order of values in errorgatecat2021-07-101-1/+1
|/ / / / | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | / clangformatgatecat2021-07-081-2/+1
| |_|/ |/| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #751 from trabucayre/gw1ns-2gatecat2021-07-063-7/+8
|\ \ \ | | | | | | | | add support for GW1NS-2 family
| * | | .cirrus/Dockerfile.ubuntu20.04: update apycula to 0.0.1a9Gwenhael Goavec-Merou2021-07-061-1/+1
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| * | | add support for GW1NS-2 familyGwenhael Goavec-Merou2021-07-062-6/+7
| | |/ | |/| | | | | | | Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
* | | Merge pull request #754 from YosysHQ/gatecat/ecp5-dcsgatecat2021-07-064-11/+55
|\ \ \ | | | | | | | | ecp5: Add DCSC support
| * | | ecp5: Add DCSC supportgatecat2021-07-064-11/+55
| |/ / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #752 from YosysHQ/gatecat/du-mem-errorgatecat2021-07-061-1/+2
|\ \ \ | | | | | | | | design_utils: Fix memory error
| * | | design_utils: Fix memory errorgatecat2021-07-061-1/+2
| |/ / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #750 from YosysHQ/gatecat/io-improvegatecat2021-07-0610-59/+136
|\ \ \ | |/ / |/| | IO improvements for OBUFTDS
| * | interchange: Allow pseudo pip wires to overlap with bound site wires on the ↵gatecat2021-07-063-17/+13
| | | | | | | | | | | | | | | | | | same net Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Dump pre-bound routes when routing fails in debug modegatecat2021-07-061-1/+11
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Improve search for PAD-attached belsgatecat2021-07-062-41/+32
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: tests: add obuftds testAlessandro Comodi2021-07-066-0/+80
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #748 from acomodi/fix-phys-net-writinggatecat2021-07-021-2/+13
|\ \ | |/ |/| interchange: phys: skip only nets writing on disconnected out ports
| * interchange: phys: skip only nets writing on disconnected out portsAlessandro Comodi2021-07-021-2/+13
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #747 from cr1901/machxo2gatecat2021-07-019-13/+140
|\ | | | | MachXO2 Checkpoint 1
| * machxo2: Fix packing for directly-connected DFFs.William D. Jones2021-07-013-9/+28
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| * machxo2: Add VHDL primitives, demo, and script.William D. Jones2021-07-014-0/+81
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| * machxo2: Add a special case for pips whose config bits are in multipleWilliam D. Jones2021-07-011-0/+12
| | | | | | | | tiles.
| * machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.William D. Jones2021-07-011-2/+17
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| * machxo2: Set Pip and Wire delays to reasonable fake values mirroringWilliam D. Jones2021-07-011-2/+2
| | | | | | | | estimateDelay.
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