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* ci: remove RapidWright patchingAlessandro Comodi2021-06-241-3/+0
* interchange: ci: add RW patch for missing cell bel mapsAlessandro Comodi2021-06-111-0/+3
* ci: Bump mistral versiongatecat2021-06-051-1/+1
* Remove redundant code after hashlib movegatecat2021-06-021-1/+1
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-011-1/+1
* ci: Use GH only for Mistral and fpga-interchangegatecat2021-05-151-0/+24
* ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
* interchange: Pin prjoxide commitgatecat2021-04-091-0/+2
* [interchange] Update interchange CI for new chipdb change.Keith Rothman2021-04-011-1/+1
* interchange: Fix nexus cmake review commentsgatecat2021-03-311-7/+7
* ci: Build prjoxide only for LIFCLgatecat2021-03-301-6/+7
* interchange: Add Nexus to CIgatecat2021-03-301-0/+8
* gh-actions: better yosys caching based on versionAlessandro Comodi2021-03-261-2/+2
* gh-actions: use ccache and build tools before running testsAlessandro Comodi2021-03-251-39/+43
* gh-actions: interchange: multiple jobs, one for each deviceAlessandro Comodi2021-03-241-2/+2
* [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-231-1/+1
* Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-1/+1
* Increment required python-fpga-interchange version.Keith Rothman2021-03-221-1/+1
* github-actions: use capnp v0.8.0Alessandro Comodi2021-03-161-3/+3
* github-actions: pin python-fpga-interchange to tagAlessandro Comodi2021-03-161-1/+2
* github-actions: add basic CI to test FPGA interchangeAlessandro Comodi2021-03-161-0/+47
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