diff options
Diffstat (limited to 'machxo2')
| -rw-r--r-- | machxo2/cells.cc | 131 |
1 files changed, 59 insertions, 72 deletions
diff --git a/machxo2/cells.cc b/machxo2/cells.cc index 534d8e3c..bbe3f2d6 100644 --- a/machxo2/cells.cc +++ b/machxo2/cells.cc @@ -25,19 +25,6 @@ NEXTPNR_NAMESPACE_BEGIN -void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir) -{ - IdString id = ctx->id(name); - NPNR_ASSERT(cell->ports.count(id) == 0); - cell->ports[id] = PortInfo{id, nullptr, dir}; -} - -void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir) -{ - NPNR_ASSERT(cell->ports.count(id) == 0); - cell->ports[id] = PortInfo{id, nullptr, dir}; -} - std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name) { static int auto_idx = 0; @@ -64,72 +51,72 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std:: new_cell->params[id_CCU2_INJECT1_1] = std::string("YES"); new_cell->params[id_WREMUX] = std::string("INV"); - add_port(ctx, new_cell.get(), id_A0, PORT_IN); - add_port(ctx, new_cell.get(), id_B0, PORT_IN); - add_port(ctx, new_cell.get(), id_C0, PORT_IN); - add_port(ctx, new_cell.get(), id_D0, PORT_IN); - - add_port(ctx, new_cell.get(), id_A1, PORT_IN); - add_port(ctx, new_cell.get(), id_B1, PORT_IN); - add_port(ctx, new_cell.get(), id_C1, PORT_IN); - add_port(ctx, new_cell.get(), id_D1, PORT_IN); - - add_port(ctx, new_cell.get(), id_M0, PORT_IN); - add_port(ctx, new_cell.get(), id_M1, PORT_IN); - - add_port(ctx, new_cell.get(), id_FCI, PORT_IN); - add_port(ctx, new_cell.get(), id_FXA, PORT_IN); - add_port(ctx, new_cell.get(), id_FXB, PORT_IN); - - add_port(ctx, new_cell.get(), id_CLK, PORT_IN); - add_port(ctx, new_cell.get(), id_LSR, PORT_IN); - add_port(ctx, new_cell.get(), id_CE, PORT_IN); - - add_port(ctx, new_cell.get(), id_DI0, PORT_IN); - add_port(ctx, new_cell.get(), id_DI1, PORT_IN); - - add_port(ctx, new_cell.get(), id_WD0, PORT_IN); - add_port(ctx, new_cell.get(), id_WD1, PORT_IN); - add_port(ctx, new_cell.get(), id_WAD0, PORT_IN); - add_port(ctx, new_cell.get(), id_WAD1, PORT_IN); - add_port(ctx, new_cell.get(), id_WAD2, PORT_IN); - add_port(ctx, new_cell.get(), id_WAD3, PORT_IN); - add_port(ctx, new_cell.get(), id_WRE, PORT_IN); - add_port(ctx, new_cell.get(), id_WCK, PORT_IN); - - add_port(ctx, new_cell.get(), id_F0, PORT_OUT); - add_port(ctx, new_cell.get(), id_Q0, PORT_OUT); - add_port(ctx, new_cell.get(), id_F1, PORT_OUT); - add_port(ctx, new_cell.get(), id_Q1, PORT_OUT); - - add_port(ctx, new_cell.get(), id_FCO, PORT_OUT); - add_port(ctx, new_cell.get(), id_OFX0, PORT_OUT); - add_port(ctx, new_cell.get(), id_OFX1, PORT_OUT); - - add_port(ctx, new_cell.get(), id_WDO0, PORT_OUT); - add_port(ctx, new_cell.get(), id_WDO1, PORT_OUT); - add_port(ctx, new_cell.get(), id_WDO2, PORT_OUT); - add_port(ctx, new_cell.get(), id_WDO3, PORT_OUT); - add_port(ctx, new_cell.get(), id_WADO0, PORT_OUT); - add_port(ctx, new_cell.get(), id_WADO1, PORT_OUT); - add_port(ctx, new_cell.get(), id_WADO2, PORT_OUT); - add_port(ctx, new_cell.get(), id_WADO3, PORT_OUT); + new_cell->addInput(id_A0); + new_cell->addInput(id_B0); + new_cell->addInput(id_C0); + new_cell->addInput(id_D0); + + new_cell->addInput(id_A1); + new_cell->addInput(id_B1); + new_cell->addInput(id_C1); + new_cell->addInput(id_D1); + + new_cell->addInput(id_M0); + new_cell->addInput(id_M1); + + new_cell->addInput(id_FCI); + new_cell->addInput(id_FXA); + new_cell->addInput(id_FXB); + + new_cell->addInput(id_CLK); + new_cell->addInput(id_LSR); + new_cell->addInput(id_CE); + + new_cell->addInput(id_DI0); + new_cell->addInput(id_DI1); + + new_cell->addInput(id_WD0); + new_cell->addInput(id_WD1); + new_cell->addInput(id_WAD0); + new_cell->addInput(id_WAD1); + new_cell->addInput(id_WAD2); + new_cell->addInput(id_WAD3); + new_cell->addInput(id_WRE); + new_cell->addInput(id_WCK); + + new_cell->addOutput(id_F0); + new_cell->addOutput(id_Q0); + new_cell->addOutput(id_F1); + new_cell->addOutput(id_Q1); + + new_cell->addOutput(id_FCO); + new_cell->addOutput(id_OFX0); + new_cell->addOutput(id_OFX1); + + new_cell->addOutput(id_WDO0); + new_cell->addOutput(id_WDO1); + new_cell->addOutput(id_WDO2); + new_cell->addOutput(id_WDO3); + new_cell->addOutput(id_WADO0); + new_cell->addOutput(id_WADO1); + new_cell->addOutput(id_WADO2); + new_cell->addOutput(id_WADO3); } else if (type == id_FACADE_IO) { new_cell->params[id_DIR] = std::string("INPUT"); new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33"); - add_port(ctx, new_cell.get(), "PAD", PORT_INOUT); - add_port(ctx, new_cell.get(), "I", PORT_IN); - add_port(ctx, new_cell.get(), "EN", PORT_IN); - add_port(ctx, new_cell.get(), "O", PORT_OUT); + new_cell->addInout(ctx->id("PAD")); + new_cell->addInput(ctx->id("I")); + new_cell->addInput(ctx->id("EN")); + new_cell->addOutput(ctx->id("O")); } else if (type == id_LUT4) { new_cell->params[id_INIT] = Property(0, 16); - add_port(ctx, new_cell.get(), id_A, PORT_IN); - add_port(ctx, new_cell.get(), id_B, PORT_IN); - add_port(ctx, new_cell.get(), id_C, PORT_IN); - add_port(ctx, new_cell.get(), id_D, PORT_IN); - add_port(ctx, new_cell.get(), id_Z, PORT_OUT); + new_cell->addInput(id_A); + new_cell->addInput(id_B); + new_cell->addInput(id_C); + new_cell->addInput(id_D); + new_cell->addOutput(id_Z); } else { log_error("unable to create MachXO2 cell of type %s", type.c_str(ctx)); } |