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-rw-r--r--ice40/arch.cc26
-rw-r--r--ice40/arch.h22
-rw-r--r--ice40/arch_place.cc10
-rw-r--r--ice40/chains.cc4
-rw-r--r--ice40/main.cc24
-rw-r--r--ice40/pack.cc12
-rw-r--r--ice40/pcf.cc2
7 files changed, 50 insertions, 50 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 43308a52..152d70a3 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -67,9 +67,9 @@ static const ChipInfoPOD *get_chip_info(ArchArgs::ArchArgsTypes chip)
return ptr->get();
}
-bool Arch::isAvailable(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; }
+bool Arch::is_available(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; }
-std::vector<std::string> Arch::getSupportedPackages(ArchArgs::ArchArgsTypes chip)
+std::vector<std::string> Arch::get_supported_packages(ArchArgs::ArchArgsTypes chip)
{
const ChipInfoPOD *chip_info = get_chip_info(chip);
std::vector<std::string> packages;
@@ -350,7 +350,7 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
return ret;
}
-bool Arch::isBelLocked(BelId bel) const
+bool Arch::is_bel_locked(BelId bel) const
{
const BelConfigPOD *bel_config = nullptr;
for (auto &bel_cfg : chip_info->bel_config) {
@@ -493,7 +493,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
// -----------------------------------------------------------------------
-BelId Arch::getPackagePinBel(const std::string &pin) const
+BelId Arch::get_package_pin_bel(const std::string &pin) const
{
for (auto &ppin : package_info->pins) {
if (ppin.name.get() == pin) {
@@ -505,7 +505,7 @@ BelId Arch::getPackagePinBel(const std::string &pin) const
return BelId();
}
-std::string Arch::getBelPackagePin(BelId bel) const
+std::string Arch::get_bel_package_pin(BelId bel) const
{
for (auto &ppin : package_info->pins) {
if (ppin.bel_index == bel.index) {
@@ -939,10 +939,10 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
} else if (cell->type == id_ICESTORM_RAM || cell->type == id_ICESTORM_SPRAM) {
return false;
}
- return getCellDelayInternal(cell, fromPort, toPort, delay);
+ return get_cell_delay_internal(cell, fromPort, toPort, delay);
}
-bool Arch::getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+bool Arch::get_cell_delay_internal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
for (auto &tc : chip_info->cell_timing) {
if (tc.type == cell->type.index) {
@@ -1094,12 +1094,12 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
info.clock_port = id_CLK;
info.edge = cell->lcInfo.negClk ? FALLING_EDGE : RISING_EDGE;
if (port == id_O) {
- bool has_clktoq = getCellDelayInternal(cell, id_CLK, id_O, info.clockToQ);
+ bool has_clktoq = get_cell_delay_internal(cell, id_CLK, id_O, info.clockToQ);
NPNR_ASSERT(has_clktoq);
} else {
if (port == id_I0 || port == id_I1 || port == id_I2 || port == id_I3) {
DelayInfo dlut;
- bool has_ld = getCellDelayInternal(cell, port, id_O, dlut);
+ bool has_ld = get_cell_delay_internal(cell, port, id_O, dlut);
NPNR_ASSERT(has_ld);
if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP4K || args.type == ArchArgs::LP8K ||
args.type == ArchArgs::LP384) {
@@ -1124,7 +1124,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
info.edge = bool_or_default(cell->params, id("NEG_CLK_W")) ? FALLING_EDGE : RISING_EDGE;
}
if (cell->ports.at(port).type == PORT_OUT) {
- bool has_clktoq = getCellDelayInternal(cell, info.clock_port, port, info.clockToQ);
+ bool has_clktoq = get_cell_delay_internal(cell, info.clock_port, port, info.clockToQ);
NPNR_ASSERT(has_clktoq);
} else {
info.setup.delay = 100;
@@ -1170,7 +1170,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
info.clock_port = cell->type == id_ICESTORM_SPRAM ? id_CLOCK : id_CLK;
info.edge = RISING_EDGE;
if (cell->ports.at(port).type == PORT_OUT) {
- bool has_clktoq = getCellDelayInternal(cell, info.clock_port, port, info.clockToQ);
+ bool has_clktoq = get_cell_delay_internal(cell, info.clock_port, port, info.clockToQ);
if (!has_clktoq)
info.clockToQ.delay = 100;
} else {
@@ -1194,7 +1194,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
return info;
}
-bool Arch::isGlobalNet(const NetInfo *net) const
+bool Arch::is_global_net(const NetInfo *net) const
{
if (net == nullptr)
return false;
@@ -1206,7 +1206,7 @@ void Arch::assignArchInfo()
{
for (auto &net : getCtx()->nets) {
NetInfo *ni = net.second.get();
- if (isGlobalNet(ni))
+ if (is_global_net(ni))
ni->is_global = true;
ni->is_enable = false;
ni->is_reset = false;
diff --git a/ice40/arch.h b/ice40/arch.h
index 1987f17a..1031aefa 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -399,8 +399,8 @@ struct Arch : BaseCtx
ArchArgs args;
Arch(ArchArgs args);
- static bool isAvailable(ArchArgs::ArchArgsTypes chip);
- static std::vector<std::string> getSupportedPackages(ArchArgs::ArchArgsTypes chip);
+ static bool is_available(ArchArgs::ArchArgsTypes chip);
+ static std::vector<std::string> get_supported_packages(ArchArgs::ArchArgsTypes chip);
std::string getChipName() const;
@@ -506,7 +506,7 @@ struct Arch : BaseCtx
PortType getBelPinType(BelId bel, IdString pin) const;
std::vector<IdString> getBelPins(BelId bel) const;
- bool isBelLocked(BelId bel) const;
+ bool is_bel_locked(BelId bel) const;
// -------------------------------------------------
@@ -767,8 +767,8 @@ struct Arch : BaseCtx
return range;
}
- BelId getPackagePinBel(const std::string &pin) const;
- std::string getBelPackagePin(BelId bel) const;
+ BelId get_package_pin_bel(const std::string &pin) const;
+ std::string get_bel_package_pin(BelId bel) const;
// -------------------------------------------------
@@ -818,15 +818,15 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists. This only considers combinational delays, as required by the Arch API
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
- // getCellDelayInternal is similar to the above, but without false path checks and including clock to out delays
+ // get_cell_delay_internal is similar to the above, but without false path checks and including clock to out delays
// for internal arch use only
- bool getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
+ bool get_cell_delay_internal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
// Get the TimingClockingInfo of a port
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
// Return true if a port is a net
- bool isGlobalNet(const NetInfo *net) const;
+ bool is_global_net(const NetInfo *net) const;
// -------------------------------------------------
@@ -883,7 +883,7 @@ struct Arch : BaseCtx
bool isBelLocationValid(BelId bel) const;
// Helper function for above
- bool logicCellsCompatible(const CellInfo **it, const size_t size) const;
+ bool logic_cells_compatible(const CellInfo **it, const size_t size) const;
// -------------------------------------------------
// Assign architecture-specific arguments to nets and cells, which must be
@@ -893,7 +893,7 @@ struct Arch : BaseCtx
void assignCellInfo(CellInfo *cell);
// -------------------------------------------------
- BelPin getIOBSharingPLLPin(BelId pll, IdString pll_pin) const
+ BelPin get_iob_sharing_pll_pin(BelId pll, IdString pll_pin) const
{
auto wire = getBelPinWire(pll, pll_pin);
for (auto src_bel : getWireBelPins(wire)) {
@@ -904,7 +904,7 @@ struct Arch : BaseCtx
NPNR_ASSERT_FALSE("Expected PLL pin to share an output with an SB_IO D_IN_{0,1}");
}
- int getDrivenGlobalNetwork(BelId bel) const
+ int get_driven_glb_netwk(BelId bel) const
{
NPNR_ASSERT(getBelType(bel) == id_SB_GB);
IdString glb_net = getWireName(getBelPinWire(bel, id_GLOBAL_BUFFER_OUTPUT))[2];
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index e4f302fd..a450a7df 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -27,7 +27,7 @@
NEXTPNR_NAMESPACE_BEGIN
-bool Arch::logicCellsCompatible(const CellInfo **it, const size_t size) const
+bool Arch::logic_cells_compatible(const CellInfo **it, const size_t size) const
{
bool dffs_exist = false, dffs_neg = false;
const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
@@ -81,7 +81,7 @@ bool Arch::isBelLocationValid(BelId bel) const
if (ci_other != nullptr)
bel_cells[num_cells++] = ci_other;
}
- return logicCellsCompatible(bel_cells.data(), num_cells);
+ return logic_cells_compatible(bel_cells.data(), num_cells);
} else {
CellInfo *ci = getBoundBelCell(bel);
if (ci == nullptr)
@@ -119,7 +119,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
}
bel_cells[num_cells++] = cell;
- return logicCellsCompatible(bel_cells.data(), num_cells);
+ return logic_cells_compatible(bel_cells.data(), num_cells);
} else if (cell->type == id_SB_IO) {
// Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
@@ -195,13 +195,13 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
}
}
- return getBelPackagePin(bel) != "";
+ return get_bel_package_pin(bel) != "";
} else if (cell->type == id_SB_GB) {
if (cell->gbInfo.forPadIn)
return true;
NPNR_ASSERT(cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net != nullptr);
const NetInfo *net = cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net;
- int glb_id = getDrivenGlobalNetwork(bel);
+ int glb_id = get_driven_glb_netwk(bel);
if (net->is_reset && net->is_enable)
return false;
else if (net->is_reset)
diff --git a/ice40/chains.cc b/ice40/chains.cc
index 1a042712..7eb03105 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -63,7 +63,7 @@ class ChainConstrainer
}
tile.push_back(cell);
chains.back().cells.push_back(cell);
- bool split_chain = (!ctx->logicCellsCompatible(tile.data(), tile.size())) ||
+ bool split_chain = (!ctx->logic_cells_compatible(tile.data(), tile.size())) ||
(int(chains.back().cells.size()) > max_length);
if (split_chain) {
CellInfo *passout = make_carry_pass_out((*(curr_cell - 1))->ports.at(ctx->id("COUT")));
@@ -84,7 +84,7 @@ class ChainConstrainer
if (!at_end) {
// See if we need to split chain anyway
tile.push_back(*(curr_cell + 1));
- bool split_chain_next = (!ctx->logicCellsCompatible(tile.data(), tile.size())) ||
+ bool split_chain_next = (!ctx->logic_cells_compatible(tile.data(), tile.size())) ||
(int(chains.back().cells.size()) > max_length);
tile.pop_back();
if (split_chain_next)
diff --git a/ice40/main.cc b/ice40/main.cc
index cabf6a2e..e537c2f4 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -50,29 +50,29 @@ Ice40CommandHandler::Ice40CommandHandler(int argc, char **argv) : CommandHandler
po::options_description Ice40CommandHandler::getArchOptions()
{
po::options_description specific("Architecture specific options");
- if (Arch::isAvailable(ArchArgs::LP384))
+ if (Arch::is_available(ArchArgs::LP384))
specific.add_options()("lp384", "set device type to iCE40LP384");
- if (Arch::isAvailable(ArchArgs::LP1K))
+ if (Arch::is_available(ArchArgs::LP1K))
specific.add_options()("lp1k", "set device type to iCE40LP1K");
- if (Arch::isAvailable(ArchArgs::LP4K))
+ if (Arch::is_available(ArchArgs::LP4K))
specific.add_options()("lp4k", "set device type to iCE40LP4K");
- if (Arch::isAvailable(ArchArgs::LP8K))
+ if (Arch::is_available(ArchArgs::LP8K))
specific.add_options()("lp8k", "set device type to iCE40LP8K");
- if (Arch::isAvailable(ArchArgs::HX1K))
+ if (Arch::is_available(ArchArgs::HX1K))
specific.add_options()("hx1k", "set device type to iCE40HX1K");
- if (Arch::isAvailable(ArchArgs::HX8K))
+ if (Arch::is_available(ArchArgs::HX8K))
specific.add_options()("hx4k", "set device type to iCE40HX4K");
- if (Arch::isAvailable(ArchArgs::HX4K))
+ if (Arch::is_available(ArchArgs::HX4K))
specific.add_options()("hx8k", "set device type to iCE40HX8K");
- if (Arch::isAvailable(ArchArgs::UP3K))
+ if (Arch::is_available(ArchArgs::UP3K))
specific.add_options()("up3k", "set device type to iCE40UP3K");
- if (Arch::isAvailable(ArchArgs::UP5K))
+ if (Arch::is_available(ArchArgs::UP5K))
specific.add_options()("up5k", "set device type to iCE40UP5K");
- if (Arch::isAvailable(ArchArgs::U1K))
+ if (Arch::is_available(ArchArgs::U1K))
specific.add_options()("u1k", "set device type to iCE5LP1K");
- if (Arch::isAvailable(ArchArgs::U2K))
+ if (Arch::is_available(ArchArgs::U2K))
specific.add_options()("u2k", "set device type to iCE5LP2K");
- if (Arch::isAvailable(ArchArgs::U4K))
+ if (Arch::is_available(ArchArgs::U4K))
specific.add_options()("u4k", "set device type to iCE5LP4K");
specific.add_options()("package", po::value<std::string>(), "set device package");
specific.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest");
diff --git a/ice40/pack.cc b/ice40/pack.cc
index a909b08b..18bc90aa 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -639,7 +639,7 @@ static void promote_globals(Context *ctx)
std::map<IdString, int> clock_count, reset_count, cen_count, logic_count;
for (auto net : sorted(ctx->nets)) {
NetInfo *ni = net.second;
- if (ni->driver.cell != nullptr && !ctx->isGlobalNet(ni)) {
+ if (ni->driver.cell != nullptr && !ctx->is_global_net(ni)) {
clock_count[net.first] = 0;
reset_count[net.first] = 0;
cen_count[net.first] = 0;
@@ -667,7 +667,7 @@ static void promote_globals(Context *ctx)
if (cell.second->attrs.find(ctx->id("BEL")) != cell.second->attrs.end()) {
/* If the SB_GB is locked, doesn't matter what it drives */
BelId bel = ctx->getBelByNameStr(cell.second->attrs[ctx->id("BEL")].as_string());
- int glb_id = ctx->getDrivenGlobalNetwork(bel);
+ int glb_id = ctx->get_driven_glb_netwk(bel);
if ((glb_id % 2) == 0)
resets_available--;
else if ((glb_id % 2) == 1)
@@ -766,11 +766,11 @@ static void place_plls(Context *ctx)
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) != id_ICESTORM_PLL)
continue;
- if (ctx->isBelLocked(bel))
+ if (ctx->is_bel_locked(bel))
continue;
- auto io_a_pin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_A);
- auto io_b_pin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_B);
+ auto io_a_pin = ctx->get_iob_sharing_pll_pin(bel, id_PLLOUT_A);
+ auto io_b_pin = ctx->get_iob_sharing_pll_pin(bel, id_PLLOUT_B);
auto gb_a = find_padin_gbuf(ctx, bel, id_PLLOUT_A_GLOBAL);
auto gb_b = find_padin_gbuf(ctx, bel, id_PLLOUT_B_GLOBAL);
@@ -1064,7 +1064,7 @@ static BelId cell_place_unique(Context *ctx, CellInfo *ci)
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) != ci->type)
continue;
- if (ctx->isBelLocked(bel))
+ if (ctx->is_bel_locked(bel))
continue;
IdStringList bel_name = ctx->getBelName(bel);
ci->attrs[ctx->id("BEL")] = bel_name.str(ctx);
diff --git a/ice40/pcf.cc b/ice40/pcf.cc
index 867f6165..56a4a336 100644
--- a/ice40/pcf.cc
+++ b/ice40/pcf.cc
@@ -89,7 +89,7 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
if (!nowarn)
log_warning("unmatched constraint '%s' (on line %d)\n", cell.c_str(), lineno);
} else {
- BelId pin_bel = ctx->getPackagePinBel(pin);
+ BelId pin_bel = ctx->get_package_pin_bel(pin);
if (pin_bel == BelId())
log_error("package does not have a pin named '%s' (on line %d)\n", pin.c_str(), lineno);
if (fnd_cell->second->attrs.count(ctx->id("BEL")))
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 21:32:38 +0000