diff options
Diffstat (limited to 'ice40/arch_place.cc')
| -rw-r--r-- | ice40/arch_place.cc | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index d9210378..faa6b187 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -88,40 +88,38 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) return locals.size() <= 32; } -bool isBelLocationValid(Design *design, BelId bel) +bool isBelLocationValid(Context *ctx, BelId bel) { - const Arch &chip = design->chip; - if (chip.getBelType(bel) == TYPE_ICESTORM_LC) { + if (ctx->getBelType(bel) == TYPE_ICESTORM_LC) { std::vector<const CellInfo *> cells; - for (auto bel_other : chip.getBelsAtSameTile(bel)) { - IdString cell_other = chip.getBelCell(bel_other, false); + for (auto bel_other : ctx->getBelsAtSameTile(bel)) { + IdString cell_other = ctx->getBelCell(bel_other, false); if (cell_other != IdString()) { - const CellInfo *ci_other = design->cells[cell_other]; + const CellInfo *ci_other = ctx->cells[cell_other]; cells.push_back(ci_other); } } return logicCellsCompatible(cells); } else { - IdString cellId = chip.getBelCell(bel, false); + IdString cellId = ctx->getBelCell(bel, false); if (cellId == IdString()) return true; else - return isValidBelForCell(design, design->cells.at(cellId), bel); + return isValidBelForCell(ctx, ctx->cells.at(cellId), bel); } } -bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) +bool isValidBelForCell(Context *ctx, CellInfo *cell, BelId bel) { - const Arch &chip = design->chip; if (cell->type == "ICESTORM_LC") { - assert(chip.getBelType(bel) == TYPE_ICESTORM_LC); + assert(ctx->getBelType(bel) == TYPE_ICESTORM_LC); std::vector<const CellInfo *> cells; - for (auto bel_other : chip.getBelsAtSameTile(bel)) { - IdString cell_other = chip.getBelCell(bel_other, false); + for (auto bel_other : ctx->getBelsAtSameTile(bel)) { + IdString cell_other = ctx->getBelCell(bel_other, false); if (cell_other != IdString()) { - const CellInfo *ci_other = design->cells[cell_other]; + const CellInfo *ci_other = ctx->cells[cell_other]; cells.push_back(ci_other); } } @@ -129,7 +127,7 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) cells.push_back(cell); return logicCellsCompatible(cells); } else if (cell->type == "SB_IO") { - return design->chip.getBelPackagePin(bel) != ""; + return ctx->getBelPackagePin(bel) != ""; } else if (cell->type == "SB_GB") { bool is_reset = false, is_cen = false; assert(cell->ports.at("GLOBAL_BUFFER_OUTPUT").net != nullptr); @@ -139,8 +137,8 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) if (is_enable_port(user)) is_cen = true; } - IdString glb_net = chip.getWireName( - chip.getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT)); + IdString glb_net = ctx->getWireName( + ctx->getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT)); int glb_id = std::stoi(std::string("") + glb_net.str().back()); if (is_reset && is_cen) return false; |