diff options
Diffstat (limited to 'generic')
| -rw-r--r-- | generic/arch.cc | 8 | ||||
| -rw-r--r-- | generic/arch.h | 4 |
2 files changed, 7 insertions, 5 deletions
diff --git a/generic/arch.cc b/generic/arch.cc index e867d310..a1e03210 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -435,9 +435,11 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort return false; } -IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); } - -bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; } +// Get the port class, also setting clockPort if applicable +TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const +{ + return TMG_IGNORE; +} bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } bool Arch::isBelLocationValid(BelId bel) const { return true; } diff --git a/generic/arch.h b/generic/arch.h index 0e0aec27..c5863ec3 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -215,8 +215,8 @@ struct Arch : BaseCtx DecalXY getGroupDecal(GroupId group) const; bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; - IdString getPortClock(const CellInfo *cell, IdString port) const; - bool isClockPort(const CellInfo *cell, IdString port) const; + // Get the port class, also setting clockPort if applicable + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const; bool isValidBelForCell(CellInfo *cell, BelId bel) const; bool isBelLocationValid(BelId bel) const; |