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-rw-r--r--fpga_interchange/site_router.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index c470f3f6..3252cac1 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -58,6 +58,9 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
for (CellInfo *cell : site_info->cells_in_site) {
BelId bel = cell->bel;
for (const auto &pin_pair : cell->cell_bel_pins) {
+ if (!cell->ports.count(pin_pair.first))
+ log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
+ pin_pair.first.c_str(ctx));
const PortInfo &port = cell->ports.at(pin_pair.first);
NPNR_ASSERT(port.net != nullptr);