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diff --git a/fpga_interchange/README.md b/fpga_interchange/README.md index 78dd23ce..f5530c0e 100644 --- a/fpga_interchange/README.md +++ b/fpga_interchange/README.md @@ -25,7 +25,7 @@ island based FPGA. It consists of three primary file formats: design, a partially or fully placed design, and a partially or fully routed design. -### Current status +### Current development status This architecture implementation can be compiled in conjunction with a FPGA interchange device database, and the outputs from @@ -36,157 +36,43 @@ library. The current implementation is missing essential features for place and route. As these features are added, this implementation will become more useful. - - [ ] The router lookahead is missing, meaning that router runtime - performance will be terrible. - - [ ] Pseudo pips (e.g. pips that consume BELs and or site resources) should - block their respective resources. This effects designs that have some - routing in place before placement. - - [ ] Pseudo site pips (e.g. site pips that route through BELs) should block - their respective resources. Without this, using some pseudo site pips - could result in invalid placements. - - [ ] Implemented site router lacks important features for tight packing. - Also the current site router is relatively untested, so legal - configurations may be rejected and illegal configurations may be - accepted. - [ ] Logical netlist macro expansion is not implemented, meaning that any macro primitives are unplaceable. Common macro primitives examples are differential IO buffers (IBUFDS) and some LUT RAM (e.g. RAM64X1D). - [ ] Timing information is missing from the FPGA interchange device database, so it is also currently missing from the FPGA interchange architecture. Once timing information is added to the device database - schema, it needs to be added to the architecture. -#### FPGA interchange fabrics - -Currently only Xilinx 7-series, UltraScale and UltraScale+ fabrics have a +#### Weaknesses of current implementation + +Initial development on the following features is started, but needs more +refinement. + + - [ ] BEL validity checking is too expensive. The majority of the runtime + is currently in the LUT rotation. Profiling, optimization and + algorithm review is likely required to bring strict legalisation + runtimes into expected levels. + - [ ] The router lookahead is disabled by default. Without the lookahead, + router runtime is terrible. However the current lookahead + implementation is slow to compute and memory intensive, hence why it is + disabled by default. + - [ ] Pseudo pips (e.g. pips that consume BELs and or site resources) and + pseudo site pips (e.g. site pips that route through BELs) consume site + wires to indicate that they block some resources. This covers many + validity check cases, but misses some. In particular, when a pseudo + pip / pseudo site pip has an implication on the constraint system (e.g. + LUT on a LUT-RAM BEL), an edge may be allowed incorrectly, resulting + in an illegal design. + +### FPGA interchange fabrics + +Xilinx 7-series, UltraScale and UltraScale+ fabrics have a device database generator, via [RapidWright](https://github.com/Xilinx/RapidWright). -##### Artix 35T example - -Install capnproto if not already installed: -``` -# Or equivalent for your local system. -sudo apt-get install capnproto libcapnp-dev -``` - -Install capnproto-java if not already installed: -``` -git clone https://github.com/capnproto/capnproto-java.git -cd capnproto-java -make -sudo make install -``` - -##### Makefile-driven BBA creation - -In `${NEXTPNR_DIR}/fpga_interchange/examples/create_bba` is a Makefile that -should compile nextpnr and create a Xilinx A35 chipdb if java, capnproto and -capnproto-java are installed. - -Instructions: -``` -cd ${NEXTPNR_DIR}/fpga_interchange/examples/create_bba -make -``` - -This will create a virtual env in -`${NEXTPNR_DIR}/fpga_interchange/examples/create_bba/build/env` that has the -python-fpga-interchange library installed. Before running the design examples, -enter the virtual env, e.g.: - -``` -source ${NEXTPNR_DIR}/fpga_interchange/examples/create_bba/build/env/bin/activate -``` - -The chipdb will be written to `${NEXTPNR_DIR}/fpga_interchange/examples/create_bba/build/xc7a35.bin` -once completed. - -##### Manual BBA creation - -This covers the manual set of steps to create a Xilinx A35 chipdb. - -Download RapidWright and generate the device database. -``` -# FIXME: Use main branch once interchange branch is merged. -git clone -b interchange https://github.com/Xilinx/RapidWright.git -cd RapidWright -make update_jars - -# FIXME: Current RapidWright jars generate database with duplicate PIPs -# https://github.com/Xilinx/RapidWright/issues/127 -# Remove this wget once the latest RapidWright JAR is published. -wget https://github.com/Xilinx/RapidWright/releases/download/v2020.2.1-beta/rapidwright-api-lib-2020.2.1_update1.jar -mv rapidwright-api-lib-2020.2.1_update1.jar jars/rapidwright-api-lib-2020.2.0.jar - -./scripts/invoke_rapidwright.sh com.xilinx.rapidwright.interchange.DeviceResourcesExample xc7a35tcpg236-1 -export RAPIDWRIGHT_PATH=$(pwd) -``` - -Set `INTERCHANGE_DIR` to point to 3rdparty/fpga-interchange-schema: -``` -export INTERCHANGE_DIR=$(NEXTPNR_DIR)/3rdparty/fpga-interchange-schema/interchange -``` - -Install python FPGA interchange library. -``` -git clone https://github.com/SymbiFlow/python-fpga-interchange.git -cd python-fpga-interchange -pip install -r requirements.txt -``` - -Patch device database with cell constraints and LUT annotations: -``` -python3 -mfpga_interchange.patch \ - --schema_dir ${INTERCHANGE_DIR} \ - --schema device \ - --patch_path constraints \ - --patch_format yaml \ - ${RAPIDWRIGHT_PATH}/xc7a35tcpg236-1.device \ - test_data/series7_constraints.yaml \ - xc7a35tcpg236-1_constraints.device -python3 -mfpga_interchange.patch \ - --schema_dir ${INTERCHANGE_DIR} \ - --schema device \ - --patch_path lutDefinitions \ - --patch_format yaml \ - xc7a35tcpg236-1_constraints.device \ - test_data/series7_luts.yaml \ - xc7a35tcpg236-1_constraints_luts.device -``` - -Generate nextpnr BBA and constids.inc from device database: -``` -python3 -mfpga_interchange.nextpnr_emit \ - --schema_dir ${INTERCHANGE_DIR} \ - --output_dir ${NEXTPNR_DIR}/fpga_interchange/ \ - --bel_bucket_seeds test_data/series7_bel_buckets.yaml \ - --device xc7a35tcpg236-1_constraints_luts.device \ -``` - -Build nextpnr: - -``` -cd ${NEXTPNR_DIR} -cmake -DARCH=fpga_interchange . -make -j -``` - -Compile generated BBA: -``` -bba/bbasm -l fpga_interchange/chipdb.bba fpga_interchange/chipdb.bin -``` - -Run nextpnr archcheck: -``` -./nextpnr-fpga_interchange --chipdb fpga_interchange/chipdb.bin --test -``` - -Once nextpnr can complete the place and route task and output the physical -netlist, RapidWright can be used to generate a DCP suitable for bitstream -output and DRC checks. - -``` -${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh \ - com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \ - <logical netlist file> <physical netlist file> <XDC file> <output DCP> -``` +A Lattice Nexus device database is being worked on, via +[prjoxide](https://github.com/gatecat/prjoxide). + +### FPGA interchange build system + +Construction of chipdb's is currently integrated into nextpnr's CMake build +system. See fpga\_interchange/examples/README.md for more details. |