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-rw-r--r--ecp5/arch.cc2
-rw-r--r--ecp5/bitstream.cc2
2 files changed, 4 insertions, 0 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 861aeef2..1479e6ca 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -568,6 +568,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
if (port == id_O)
return TMG_STARTPOINT;
return TMG_IGNORE;
+ } else if (cell->type == id_DCCA) {
+ return TMG_IGNORE;
} else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
}
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index a1edf9e5..f04b1269 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -294,6 +294,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
+ } else if (ci->type == ctx->id("DCCA")) {
+ // Nothing to do
} else {
NPNR_ASSERT_FALSE("unsupported cell type");
}