diff options
Diffstat (limited to 'ecp5/bitstream.cc')
| -rw-r--r-- | ecp5/bitstream.cc | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index d6b1c701..bef149a4 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -701,9 +701,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex auto tiles = ctx->getTilesAtLocation(y, x); for (auto tile : tiles) { std::string type = tile.second; - if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { + if (type.find("BANKREF") != std::string::npos) { int bank = std::stoi(type.substr(7)); - if (bankVcc.find(bank) != bankVcc.end()) { + if (bank == 8 && ctx->settings.count(ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"))) { + std::string vcc = str_or_default(ctx->settings, ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE")); + vcc.at(1) = 'V'; + cc.tiles[tile.first].add_enum("BANK.VCCIO", vcc); + } else if (bankVcc.find(bank) != bankVcc.end()) { if (bankVcc[bank] == IOVoltage::VCC_1V35) cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2"); else @@ -1404,6 +1408,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG"); cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_"); } else if (ci->type == id_USRMCLK) { + if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE") + log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n"); cc.tiles[ctx->getTileByType("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK"); } else if (ci->type == id_GSR) { cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum( @@ -1485,6 +1491,29 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } } + // Add some SYSCONFIG settings + const std::string prefix = "arch.sysconfig."; + for (auto &setting : ctx->settings) { + std::string key = setting.first.str(ctx); + if (key.substr(0, prefix.length()) != prefix) + continue; + key = key.substr(prefix.length()); + std::string value = setting.second.as_string(); + if (key == "SLAVE_SPI_PORT" || key == "DONE_EX") { + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value); + cc.tiles[ctx->getTileByType("EFB2_PICB0")].add_enum("SYSCONFIG." + key, value); + } else if (key == "SLAVE_PARALLEL_PORT" || key == "BACKGROUND_RECONFIG" || key == "WAKE_UP") { + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value); + } else if (key == "MASTER_SPI_PORT") { + cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value); + } else if (key == "TRANSFR") { + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value); + cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value); + } else { + cc.sysconfig[key] = value; + } + } + // Fixup tile names fix_tile_names(ctx, cc); // Configure chip |