1 files changed, 71 insertions, 5 deletions

diff --git a/ecp5/arch.h b/ecp5/arch.h
index aa3c5348..a68673f4 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -71,7 +71,7 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     LocationPOD rel_src_loc, rel_dst_loc;
     int32_t src_idx, dst_idx;
-    int32_t delay;
+    int32_t timing_class;
     int16_t tile_type;
     int8_t pip_type;
     int8_t padding_0;
@@ -151,6 +151,44 @@ NPNR_PACKED_STRUCT(struct GlobalInfoPOD {
     int16_t spine_col;
 });
 
+NPNR_PACKED_STRUCT(struct CellPropDelayPOD {
+    int32_t from_port;
+    int32_t to_port;
+    int32_t min_delay;
+    int32_t max_delay;
+});
+
+NPNR_PACKED_STRUCT(struct CellSetupHoldPOD {
+    int32_t sig_port;
+    int32_t clock_port;
+    int32_t min_setup;
+    int32_t max_setup;
+    int32_t min_hold;
+    int32_t max_hold;
+});
+
+NPNR_PACKED_STRUCT(struct CellTimingPOD {
+    int32_t cell_type;
+    int32_t num_prop_delays;
+    int32_t num_setup_holds;
+    RelPtr<CellPropDelayPOD> prop_delays;
+    RelPtr<CellSetupHoldPOD> setup_holds;
+});
+
+NPNR_PACKED_STRUCT(struct PipDelayPOD {
+    int32_t min_base_delay;
+    int32_t max_base_delay;
+    int32_t min_fanout_adder;
+    int32_t max_fanout_adder;
+});
+
+NPNR_PACKED_STRUCT(struct SpeedGradePOD {
+    int32_t num_cell_timings;
+    int32_t num_pip_classes;
+    RelPtr<CellTimingPOD> cell_timings;
+    RelPtr<PipDelayPOD> pip_classes;
+});
+
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     int32_t width, height;
     int32_t num_tiles;
@@ -163,6 +201,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<PackageInfoPOD> package_info;
     RelPtr<PIOInfoPOD> pio_info;
     RelPtr<TileInfoPOD> tile_info;
+    RelPtr<SpeedGradePOD> speed_grades;
 });
 
 #if defined(_MSC_VER)
@@ -400,13 +439,20 @@ struct ArchArgs
         LFE5UM5G_85F,
     } type = NONE;
     std::string package;
-    int speed = 6;
+    enum SpeedGrade
+    {
+        SPEED_6 = 0,
+        SPEED_7,
+        SPEED_8,
+        SPEED_8_5G,
+    } speed = SPEED_6;
 };
 
 struct Arch : BaseCtx
 {
     const ChipInfoPOD *chip_info;
     const PackageInfoPOD *package_info;
+    const SpeedGradePOD *speed_grade;
 
     mutable std::unordered_map<IdString, BelId> bel_by_name;
     mutable std::unordered_map<IdString, WireId> wire_by_name;
@@ -415,6 +461,7 @@ struct Arch : BaseCtx
     std::vector<CellInfo *> bel_to_cell;
     std::unordered_map<WireId, NetInfo *> wire_to_net;
     std::unordered_map<PipId, NetInfo *> pip_to_net;
+    std::unordered_map<WireId, int> wire_fanout;
 
     ArchArgs args;
     Arch(ArchArgs args);
@@ -597,6 +644,7 @@ struct Arch : BaseCtx
 
         auto pip = it->second.pip;
         if (pip != PipId()) {
+            wire_fanout[getPipSrcWire(pip)]--;
             pip_to_net[pip] = nullptr;
         }
 
@@ -633,7 +681,8 @@ struct Arch : BaseCtx
     DelayInfo getWireDelay(WireId wire) const
     {
         DelayInfo delay;
-        delay.delay = 0;
+        delay.min_delay = 0;
+        delay.max_delay = 0;
         return delay;
     }
 
@@ -686,6 +735,7 @@ struct Arch : BaseCtx
         NPNR_ASSERT(pip_to_net[pip] == nullptr);
 
         pip_to_net[pip] = net;
+        wire_fanout[getPipSrcWire(pip)]++;
 
         WireId dst;
         dst.index = locInfo(pip)->pip_data[pip.index].dst_idx;
@@ -700,6 +750,7 @@ struct Arch : BaseCtx
     {
         NPNR_ASSERT(pip != PipId());
         NPNR_ASSERT(pip_to_net[pip] != nullptr);
+        wire_fanout[getPipSrcWire(pip)]--;
 
         WireId dst;
         dst.index = locInfo(pip)->pip_data[pip.index].dst_idx;
@@ -772,7 +823,17 @@ struct Arch : BaseCtx
     {
         DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
-        delay.delay = locInfo(pip)->pip_data[pip.index].delay;
+        int fanout = 0;
+        auto fnd_fanout = wire_fanout.find(getPipSrcWire(pip));
+        if (fnd_fanout != wire_fanout.end())
+            fanout = fnd_fanout->second;
+        NPNR_ASSERT(locInfo(pip)->pip_data[pip.index].timing_class < speed_grade->num_pip_classes);
+        delay.min_delay =
+                speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay +
+                fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
+        delay.max_delay =
+                speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay +
+                fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
         return delay;
     }
 
@@ -862,7 +923,8 @@ struct Arch : BaseCtx
     DelayInfo getDelayFromNS(float ns) const
     {
         DelayInfo del;
-        del.delay = delay_t(ns * 1000);
+        del.min_delay = delay_t(ns * 1000);
+        del.max_delay = delay_t(ns * 1000);
         return del;
     }
     uint32_t getDelayChecksum(delay_t v) const { return v; }
@@ -895,6 +957,10 @@ struct Arch : BaseCtx
     // Return true if a port is a net
     bool isGlobalNet(const NetInfo *net) const;
 
+    bool getDelayFromTimingDatabase(IdString tctype, IdString from, IdString to, DelayInfo &delay) const;
+    void getSetupHoldFromTimingDatabase(IdString tctype, IdString clock, IdString port, DelayInfo &setup,
+                                        DelayInfo &hold) const;
+
     // -------------------------------------------------
     // Placement validity checks
     bool isValidBelForCell(CellInfo *cell, BelId bel) const;