2 files changed, 4 insertions, 12 deletions
diff --git a/dummy/arch.cc b/dummy/arch.cc
index 4adff2ca..afd1d638 100644
--- a/dummy/arch.cc
+++ b/dummy/arch.cc
@@ -181,20 +181,13 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
 
 // ---------------------------------------------------------------
 
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
-                        IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
 {
     return false;
 }
 
-IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
-{
-    return IdString();
-}
+IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); }
 
-bool Arch::isClockPort(const CellInfo *cell, IdString port) const
-{
-    return false;
-}
+bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
 
 NEXTPNR_NAMESPACE_END
diff --git a/dummy/arch.h b/dummy/arch.h
index 2a778689..56d90d52 100644
--- a/dummy/arch.h
+++ b/dummy/arch.h
@@ -144,8 +144,7 @@ struct Arch : BaseCtx
     std::unordered_set<WireId> wireGraphicsReload;
     std::unordered_set<PipId> pipGraphicsReload;
 
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
-                      delay_t &delay) const;
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
     IdString getPortClock(const CellInfo *cell, IdString port) const;
     bool isClockPort(const CellInfo *cell, IdString port) const;
 };