diff options
Diffstat (limited to 'cyclonev')
| -rw-r--r-- | cyclonev/arch.cc | 2 | ||||
| -rw-r--r-- | cyclonev/arch.h | 2 | ||||
| -rw-r--r-- | cyclonev/lab.cc | 6 |
3 files changed, 6 insertions, 4 deletions
diff --git a/cyclonev/arch.cc b/cyclonev/arch.cc index d8464ca2..98a09d3b 100644 --- a/cyclonev/arch.cc +++ b/cyclonev/arch.cc @@ -249,6 +249,7 @@ WireId Arch::add_wire(int x, int y, IdString name, uint64_t flags) z++; wires[id].name_override = name; wires[id].flags = flags; + npnr_wirebyname[full_name] = id; return id; } } @@ -263,6 +264,7 @@ PipId Arch::add_pip(WireId src, WireId dst) void Arch::add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire) { auto &b = bel_data(bel); + NPNR_ASSERT(!b.pins.count(pin)); b.pins[pin].dir = dir; b.pins[pin].wire = wire; diff --git a/cyclonev/arch.h b/cyclonev/arch.h index 5ecba367..15c647aa 100644 --- a/cyclonev/arch.h +++ b/cyclonev/arch.h @@ -278,7 +278,7 @@ struct Arch : BaseArch<ArchRanges> WireId getWireByName(IdStringList name) const override; IdStringList getWireName(WireId wire) const override; DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); } - const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return empty_belpin_list; } + const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return wires.at(wire).bel_pins; } AllWireRange getWires() const override { return AllWireRange(wires); } // ------------------------------------------------- diff --git a/cyclonev/lab.cc b/cyclonev/lab.cc index 55602da4..a4619a8c 100644 --- a/cyclonev/lab.cc +++ b/cyclonev/lab.cc @@ -72,8 +72,8 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) // Carry/share chain arch->add_bel_pin(bel, id_CIN, PORT_IN, carry_in); arch->add_bel_pin(bel, id_SHAREIN, PORT_IN, share_in); - arch->add_bel_pin(bel, id_CIN, PORT_OUT, carry_in); - arch->add_bel_pin(bel, id_SHAREIN, PORT_OUT, share_out); + arch->add_bel_pin(bel, id_COUT, PORT_OUT, carry_out); + arch->add_bel_pin(bel, id_SHAREOUT, PORT_OUT, share_out); // Combinational output WireId comb_out = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i))); arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, comb_out); @@ -93,7 +93,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z))); sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z))); // Muxes - three CLK/ENA per LAB, two ACLR - for (int j = 0; j < 3; i++) { + for (int j = 0; j < 3; j++) { arch->add_pip(lab.clk_wires[j], sel_clk[i]); arch->add_pip(lab.ena_wires[j], sel_ena[i]); if (j < 2) |