diff options
Diffstat (limited to 'common')
| -rw-r--r-- | common/timing.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/common/timing.cc b/common/timing.cc index 7ab24c25..002ccda9 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -593,7 +593,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p if (print_path) { auto print_path_report = [ctx](ClockPair &clocks, PortRefVector &crit_path) { - delay_t total = 0; + delay_t total = 0, logic_total = 0, route_total = 0; auto &front = crit_path.front(); auto &front_port = front->cell->ports.at(front->port); auto &front_driver = front_port.net->driver; @@ -609,6 +609,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p clockInfo.edge == clocks.start.edge) { last_port = clockInfo.clock_port; total += clockInfo.clockToQ.maxDelay(); + logic_total += clockInfo.clockToQ.maxDelay(); break; } } @@ -625,14 +626,16 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p if (last_port == driver.port) { // Case where we start with a STARTPOINT etc comb_delay = ctx->getDelayFromNS(0); - } else if (total == 0) { + } else { ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay); } total += comb_delay.maxDelay(); + logic_total += comb_delay.maxDelay(); log_info("%4.1f %4.1f Source %s.%s\n", ctx->getDelayNS(comb_delay.maxDelay()), ctx->getDelayNS(total), driver_cell->name.c_str(ctx), driver.port.c_str(ctx)); auto net_delay = ctx->getNetinfoRouteDelay(net, *sink); total += net_delay; + route_total += net_delay; auto driver_loc = ctx->getBelLocation(driver_cell->bel); auto sink_loc = ctx->getBelLocation(sink_cell->bel); log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(net_delay), @@ -666,9 +669,11 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0); delay_t setup = sinkClockInfo.setup.maxDelay(); total += setup; + logic_total += setup; log_info("%4.1f %4.1f Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total), crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx)); } + log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total)); }; for (auto &clock : clock_reports) { |