1 files changed, 116 insertions, 0 deletions

diff --git a/common/nextpnr.h b/common/nextpnr.h
index 4434c438..a6617ae4 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -194,6 +194,14 @@ struct Loc
     bool operator!=(const Loc &other) const { return (x != other.x) || (y != other.y) || (z != other.z); }
 };
 
+struct TimingConstrObjectId
+{
+    int32_t index = -1;
+
+    bool operator==(const TimingConstrObjectId &other) const { return index == other.index; }
+    bool operator!=(const TimingConstrObjectId &other) const { return index != other.index; }
+};
+
 NEXTPNR_NAMESPACE_END
 
 namespace std {
@@ -208,6 +216,15 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX Loc>
         return seed;
     }
 };
+
+template <> struct hash<NEXTPNR_NAMESPACE_PREFIX TimingConstrObjectId>
+{
+    std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX TimingConstrObjectId &obj) const noexcept
+    {
+        return hash<int>()(obj.index);
+    }
+};
+
 } // namespace std
 
 #include "archdefs.h"
@@ -266,6 +283,8 @@ struct PipMap
     PlaceStrength strength = STRENGTH_NONE;
 };
 
+struct ClockConstraint;
+
 struct NetInfo : ArchNetInfo
 {
     IdString name;
@@ -278,6 +297,10 @@ struct NetInfo : ArchNetInfo
     // wire -> uphill_pip
     std::unordered_map<WireId, PipMap> wires;
 
+    std::unique_ptr<ClockConstraint> clkconstr;
+
+    TimingConstrObjectId tmg_id;
+
     Region *region = nullptr;
 };
 
@@ -293,6 +316,7 @@ struct PortInfo
     IdString name;
     NetInfo *net;
     PortType type;
+    TimingConstrObjectId tmg_id;
 };
 
 struct CellInfo : ArchCellInfo
@@ -320,6 +344,7 @@ struct CellInfo : ArchCellInfo
     // parent.[xyz] := 0 when (constr_parent == nullptr)
 
     Region *region = nullptr;
+    TimingConstrObjectId tmg_id;
 };
 
 enum TimingPortClass
@@ -335,6 +360,68 @@ enum TimingPortClass
     TMG_IGNORE,          // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
 };
 
+enum ClockEdge
+{
+    RISING_EDGE,
+    FALLING_EDGE
+};
+
+struct TimingClockingInfo
+{
+    IdString clock_port; // Port name of clock domain
+    ClockEdge edge;
+    DelayInfo setup, hold; // Input timing checks
+    DelayInfo clockToQ;    // Output clock-to-Q time
+};
+
+struct ClockConstraint
+{
+    DelayInfo high;
+    DelayInfo low;
+    DelayInfo period;
+
+    TimingConstrObjectId domain_tmg_id;
+};
+
+struct TimingConstraintObject
+{
+    TimingConstrObjectId id;
+    enum
+    {
+        ANYTHING,
+        CLOCK_DOMAIN,
+        NET,
+        CELL,
+        CELL_PORT
+    } type;
+    IdString entity; // Name of clock net; net or cell
+    IdString port;   // Name of port on a cell
+};
+
+struct TimingConstraint
+{
+    IdString name;
+
+    enum
+    {
+        FALSE_PATH,
+        MIN_DELAY,
+        MAX_DELAY,
+        MULTICYCLE,
+    } type;
+
+    delay_t value;
+
+    std::unordered_set<TimingConstrObjectId> from;
+    std::unordered_set<TimingConstrObjectId> to;
+};
+
+inline bool operator==(const std::pair<const TimingConstrObjectId, TimingConstraint *> &a,
+                       const std::pair<TimingConstrObjectId, TimingConstraint *> &b)
+{
+    return a.first == b.first && a.second == b.second;
+}
+
 struct DeterministicRNG
 {
     uint64_t rngstate;
@@ -431,6 +518,11 @@ struct BaseCtx
         idstring_idx_to_str = new std::vector<const std::string *>;
         IdString::initialize_add(this, "", 0);
         IdString::initialize_arch(this);
+
+        TimingConstraintObject wildcard;
+        wildcard.id.index = 0;
+        wildcard.type = TimingConstraintObject::ANYTHING;
+        constraintObjects.push_back(wildcard);
     }
 
     ~BaseCtx()
@@ -524,6 +616,30 @@ struct BaseCtx
     void refreshUiPip(PipId pip) { pipUiReload.insert(pip); }
 
     void refreshUiGroup(GroupId group) { groupUiReload.insert(group); }
+
+    // --------------------------------------------------------------
+
+    // Timing Constraint API
+
+    // constraint name -> constraint
+    std::unordered_map<IdString, std::unique_ptr<TimingConstraint>> constraints;
+    // object ID -> object
+    std::vector<TimingConstraintObject> constraintObjects;
+    // object ID -> constraint
+    std::unordered_multimap<TimingConstrObjectId, TimingConstraint *> constrsFrom;
+    std::unordered_multimap<TimingConstrObjectId, TimingConstraint *> constrsTo;
+
+    TimingConstrObjectId timingWildcardObject();
+    TimingConstrObjectId timingClockDomainObject(NetInfo *clockDomain);
+    TimingConstrObjectId timingNetObject(NetInfo *net);
+    TimingConstrObjectId timingCellObject(CellInfo *cell);
+    TimingConstrObjectId timingPortObject(CellInfo *cell, IdString port);
+
+    void addConstraint(std::unique_ptr<TimingConstraint> constr);
+    void removeConstraint(IdString constrName);
+
+    // Intended to simplify Python API
+    void addClock(IdString net, float freq);
 };
 
 NEXTPNR_NAMESPACE_END