aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--ice40/chip.cc170
-rw-r--r--ice40/chip.h84
-rw-r--r--ice40/chipdb.py31
3 files changed, 285 insertions, 0 deletions
diff --git a/ice40/chip.cc b/ice40/chip.cc
index cd427377..824829e5 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -25,6 +25,8 @@ IdString belTypeToId(BelType type)
{
if (type == TYPE_ICESTORM_LC)
return "ICESTORM_LC";
+ if (type == TYPE_ICESTORM_RAM)
+ return "ICESTORM_RAM";
if (type == TYPE_SB_IO)
return "SB_IO";
return IdString();
@@ -34,6 +36,8 @@ BelType belTypeFromId(IdString id)
{
if (id == "ICESTORM_LC")
return TYPE_ICESTORM_LC;
+ if (id == "ICESTORM_RAM")
+ return TYPE_ICESTORM_RAM;
if (id == "SB_IO")
return TYPE_SB_IO;
return TYPE_NIL;
@@ -57,6 +61,89 @@ IdString PortPinToId(PortPin type)
X(CLK)
X(SR)
+ X(MASK_0)
+ X(MASK_1)
+ X(MASK_2)
+ X(MASK_3)
+ X(MASK_4)
+ X(MASK_5)
+ X(MASK_6)
+ X(MASK_7)
+ X(MASK_8)
+ X(MASK_9)
+ X(MASK_10)
+ X(MASK_11)
+ X(MASK_12)
+ X(MASK_13)
+ X(MASK_14)
+ X(MASK_15)
+
+ X(RDATA_0)
+ X(RDATA_1)
+ X(RDATA_2)
+ X(RDATA_3)
+ X(RDATA_4)
+ X(RDATA_5)
+ X(RDATA_6)
+ X(RDATA_7)
+ X(RDATA_8)
+ X(RDATA_9)
+ X(RDATA_10)
+ X(RDATA_11)
+ X(RDATA_12)
+ X(RDATA_13)
+ X(RDATA_14)
+ X(RDATA_15)
+
+ X(WDATA_0)
+ X(WDATA_1)
+ X(WDATA_2)
+ X(WDATA_3)
+ X(WDATA_4)
+ X(WDATA_5)
+ X(WDATA_6)
+ X(WDATA_7)
+ X(WDATA_8)
+ X(WDATA_9)
+ X(WDATA_10)
+ X(WDATA_11)
+ X(WDATA_12)
+ X(WDATA_13)
+ X(WDATA_14)
+ X(WDATA_15)
+
+ X(WADDR_0)
+ X(WADDR_1)
+ X(WADDR_2)
+ X(WADDR_3)
+ X(WADDR_4)
+ X(WADDR_5)
+ X(WADDR_6)
+ X(WADDR_7)
+ X(WADDR_8)
+ X(WADDR_9)
+ X(WADDR_10)
+
+ X(RADDR_0)
+ X(RADDR_1)
+ X(RADDR_2)
+ X(RADDR_3)
+ X(RADDR_4)
+ X(RADDR_5)
+ X(RADDR_6)
+ X(RADDR_7)
+ X(RADDR_8)
+ X(RADDR_9)
+ X(RADDR_10)
+
+ X(WCLK)
+ X(WCLKE)
+ X(WE)
+
+ X(RCLK)
+ X(RCLKE)
+ X(RE)
+
X(PACKAGE_PIN)
X(LATCH_INPUT_VALUE)
X(CLOCK_ENABLE)
@@ -88,6 +175,89 @@ PortPin PortPinFromId(IdString id)
X(CLK)
X(SR)
+ X(MASK_0)
+ X(MASK_1)
+ X(MASK_2)
+ X(MASK_3)
+ X(MASK_4)
+ X(MASK_5)
+ X(MASK_6)
+ X(MASK_7)
+ X(MASK_8)
+ X(MASK_9)
+ X(MASK_10)
+ X(MASK_11)
+ X(MASK_12)
+ X(MASK_13)
+ X(MASK_14)
+ X(MASK_15)
+
+ X(RDATA_0)
+ X(RDATA_1)
+ X(RDATA_2)
+ X(RDATA_3)
+ X(RDATA_4)
+ X(RDATA_5)
+ X(RDATA_6)
+ X(RDATA_7)
+ X(RDATA_8)
+ X(RDATA_9)
+ X(RDATA_10)
+ X(RDATA_11)
+ X(RDATA_12)
+ X(RDATA_13)
+ X(RDATA_14)
+ X(RDATA_15)
+
+ X(WDATA_0)
+ X(WDATA_1)
+ X(WDATA_2)
+ X(WDATA_3)
+ X(WDATA_4)
+ X(WDATA_5)
+ X(WDATA_6)
+ X(WDATA_7)
+ X(WDATA_8)
+ X(WDATA_9)
+ X(WDATA_10)
+ X(WDATA_11)
+ X(WDATA_12)
+ X(WDATA_13)
+ X(WDATA_14)
+ X(WDATA_15)
+
+ X(WADDR_0)
+ X(WADDR_1)
+ X(WADDR_2)
+ X(WADDR_3)
+ X(WADDR_4)
+ X(WADDR_5)
+ X(WADDR_6)
+ X(WADDR_7)
+ X(WADDR_8)
+ X(WADDR_9)
+ X(WADDR_10)
+
+ X(RADDR_0)
+ X(RADDR_1)
+ X(RADDR_2)
+ X(RADDR_3)
+ X(RADDR_4)
+ X(RADDR_5)
+ X(RADDR_6)
+ X(RADDR_7)
+ X(RADDR_8)
+ X(RADDR_9)
+ X(RADDR_10)
+
+ X(WCLK)
+ X(WCLKE)
+ X(WE)
+
+ X(RCLK)
+ X(RCLKE)
+ X(RE)
+
X(PACKAGE_PIN)
X(LATCH_INPUT_VALUE)
X(CLOCK_ENABLE)
diff --git a/ice40/chip.h b/ice40/chip.h
index 57f0fa99..6113a869 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -36,6 +36,7 @@ enum BelType
{
TYPE_NIL,
TYPE_ICESTORM_LC,
+ TYPE_ICESTORM_RAM,
TYPE_SB_IO
};
@@ -58,6 +59,89 @@ enum PortPin
PIN_CLK,
PIN_SR,
+ PIN_MASK_0,
+ PIN_MASK_1,
+ PIN_MASK_2,
+ PIN_MASK_3,
+ PIN_MASK_4,
+ PIN_MASK_5,
+ PIN_MASK_6,
+ PIN_MASK_7,
+ PIN_MASK_8,
+ PIN_MASK_9,
+ PIN_MASK_10,
+ PIN_MASK_11,
+ PIN_MASK_12,
+ PIN_MASK_13,
+ PIN_MASK_14,
+ PIN_MASK_15,
+
+ PIN_RDATA_0,
+ PIN_RDATA_1,
+ PIN_RDATA_2,
+ PIN_RDATA_3,
+ PIN_RDATA_4,
+ PIN_RDATA_5,
+ PIN_RDATA_6,
+ PIN_RDATA_7,
+ PIN_RDATA_8,
+ PIN_RDATA_9,
+ PIN_RDATA_10,
+ PIN_RDATA_11,
+ PIN_RDATA_12,
+ PIN_RDATA_13,
+ PIN_RDATA_14,
+ PIN_RDATA_15,
+
+ PIN_WDATA_0,
+ PIN_WDATA_1,
+ PIN_WDATA_2,
+ PIN_WDATA_3,
+ PIN_WDATA_4,
+ PIN_WDATA_5,
+ PIN_WDATA_6,
+ PIN_WDATA_7,
+ PIN_WDATA_8,
+ PIN_WDATA_9,
+ PIN_WDATA_10,
+ PIN_WDATA_11,
+ PIN_WDATA_12,
+ PIN_WDATA_13,
+ PIN_WDATA_14,
+ PIN_WDATA_15,
+
+ PIN_WADDR_0,
+ PIN_WADDR_1,
+ PIN_WADDR_2,
+ PIN_WADDR_3,
+ PIN_WADDR_4,
+ PIN_WADDR_5,
+ PIN_WADDR_6,
+ PIN_WADDR_7,
+ PIN_WADDR_8,
+ PIN_WADDR_9,
+ PIN_WADDR_10,
+
+ PIN_RADDR_0,
+ PIN_RADDR_1,
+ PIN_RADDR_2,
+ PIN_RADDR_3,
+ PIN_RADDR_4,
+ PIN_RADDR_5,
+ PIN_RADDR_6,
+ PIN_RADDR_7,
+ PIN_RADDR_8,
+ PIN_RADDR_9,
+ PIN_RADDR_10,
+
+ PIN_WCLK,
+ PIN_WCLKE,
+ PIN_WE,
+
+ PIN_RCLK,
+ PIN_RCLKE,
+ PIN_RE,
+
PIN_PACKAGE_PIN,
PIN_LATCH_INPUT_VALUE,
PIN_CLOCK_ENABLE,
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 2d6f4ff4..3b71a6b4 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -181,6 +181,35 @@ def add_bel_io(x, y, z):
add_bel_input(bel, wire_dout_1, "D_OUT_1")
add_bel_input(bel, wire_out_en, "OUTPUT_ENABLE")
+def add_bel_ram(x, y):
+ bel = len(bel_name)
+ bel_name.append("%d_%d_ram" % (x, y))
+ bel_type.append("ICESTORM_RAM")
+
+ if (x, y, "ram/WE") in wire_names:
+ # iCE40 1K-style memories
+ y0, y1 = y, y+1
+ else:
+ # iCE40 8K-style memories
+ y1, y0 = y, y+1
+
+ for i in range(16):
+ add_bel_input (bel, wire_names[(x, y0 if i < 8 else y1, "ram/MASK_%d" % i)], "MASK_%d" % i)
+ add_bel_input (bel, wire_names[(x, y0 if i < 8 else y1, "ram/WDATA_%d" % i)], "WDATA_%d" % i)
+ add_bel_output(bel, wire_names[(x, y0 if i < 8 else y1, "ram/RDATA_%d" % i)], "RDATA_%d" % i)
+
+ for i in range(11):
+ add_bel_input(bel, wire_names[(x, y0, "ram/WADDR_%d" % i)], "WADDR_%d" % i)
+ add_bel_input(bel, wire_names[(x, y1, "ram/RADDR_%d" % i)], "RADDR_%d" % i)
+
+ add_bel_input(bel, wire_names[(x, y0, "ram/WCLK")], "WCLK")
+ add_bel_input(bel, wire_names[(x, y0, "ram/WCLKE")], "WCLKE")
+ add_bel_input(bel, wire_names[(x, y0, "ram/WE")], "WE")
+
+ add_bel_input(bel, wire_names[(x, y1, "ram/RCLK")], "RCLK")
+ add_bel_input(bel, wire_names[(x, y1, "ram/RCLKE")], "RCLKE")
+ add_bel_input(bel, wire_names[(x, y1, "ram/RE")], "RE")
+
for tile_xy, tile_type in sorted(tiles.items()):
if tile_type == "logic":
for i in range(8):
@@ -188,6 +217,8 @@ for tile_xy, tile_type in sorted(tiles.items()):
if tile_type == "io":
for i in range(2):
add_bel_io(tile_xy[0], tile_xy[1], i)
+ if tile_type == "ramb":
+ add_bel_ram(tile_xy[0], tile_xy[1])
print('#include "chip.h"')