diff options
| -rw-r--r-- | cyclonev/arch.h | 6 | ||||
| -rw-r--r-- | cyclonev/archdefs.h | 31 |
2 files changed, 37 insertions, 0 deletions
diff --git a/cyclonev/arch.h b/cyclonev/arch.h index 15c647aa..53fa4174 100644 --- a/cyclonev/arch.h +++ b/cyclonev/arch.h @@ -336,6 +336,12 @@ struct Arch : BaseArch<ArchRanges> // ------------------------------------------------- + bool is_comb_cell(IdString cell_type) const; + bool is_alm_legal(uint32_t lab, uint8_t alm) const; + bool is_lab_ctrlset_legal(uint32_t lab) const; + + // ------------------------------------------------- + static const std::string defaultPlacer; static const std::vector<std::string> availablePlacers; static const std::string defaultRouter; diff --git a/cyclonev/archdefs.h b/cyclonev/archdefs.h index 249fd3d2..d6555887 100644 --- a/cyclonev/archdefs.h +++ b/cyclonev/archdefs.h @@ -124,8 +124,39 @@ struct ArchNetInfo { }; +struct ArchPinInfo +{ + // An inverter (INV) has been pushed onto this signal + bool inverted; + // The physical bel pins that this logical pin maps to + std::vector<IdString> bel_pins; +}; + +struct NetInfo; + struct ArchCellInfo { + union + { + struct + { + // Store the nets here for fast validity checking (avoids too many map lookups in a hot path) + std::array<const NetInfo *, 7> input_sigs; + const NetInfo *comb_out; + + int lut_input_count; + int lut_bits_count; + + bool is_carry, is_shared, is_extended; + } combInfo; + struct + { + const NetInfo *clk, *ena, *aclr, *sclr, *sload, *sdata, *datain; + bool clk_inv, ena_inv, aclr_inv, sclr_inv, sload_inv; + } ffInfo; + }; + + std::unordered_map<IdString, ArchPinInfo> pin_data; }; NEXTPNR_NAMESPACE_END |