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-rw-r--r--ecp5/cells.cc17
-rw-r--r--ice40/cells.cc19
2 files changed, 34 insertions, 2 deletions
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index c630c2c3..7f9f1579 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -432,7 +432,13 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
// N.B. tristate will be dealt with below
- trio->params[ctx->id("DIR")] = std::string("BIDIR");
+ NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+ if (i == nullptr || i->driver.cell == nullptr)
+ trio->params[ctx->id("DIR")] = std::string("INPUT");
+ else {
+ log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+ trio->params[ctx->id("DIR")] = std::string("BIDIR");
+ }
replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
} else {
@@ -446,6 +452,15 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
if (dinet != nullptr && dinet->name == nxio->name)
rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN"));
+ if (ctx->nets.count(nxio->name)) {
+ int i = 0;
+ IdString new_name;
+ do {
+ new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
+ } while (ctx->nets.count(new_name));
+ rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name);
+ }
+
// Create a new top port net for accurate IO timing analysis and simulation netlists
if (ctx->ports.count(nxio->name)) {
IdString tn_netname = nxio->name;
diff --git a/ice40/cells.cc b/ice40/cells.cc
index f1901c43..d23b6c49 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -22,6 +22,7 @@
#include "cells.h"
#include "design_utils.h"
#include "log.h"
+#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -424,7 +425,14 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set
replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0"));
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
// N.B. tristate will be dealt with below
- sbio->params[ctx->id("PIN_TYPE")] = 25;
+ NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+ if (i == nullptr || i->driver.cell == nullptr)
+ sbio->params[ctx->id("PIN_TYPE")] = 1;
+ else
+ sbio->params[ctx->id("PIN_TYPE")] = 25;
+ auto pu_attr = nxio->attrs.find(ctx->id("PULLUP"));
+ if (pu_attr != nxio->attrs.end())
+ sbio->params[ctx->id("PULLUP")] = pu_attr->second;
replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0"));
replace_port(nxio, ctx->id("O"), sbio, ctx->id("D_IN_0"));
} else {
@@ -438,6 +446,15 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set
if (dinet != nullptr && dinet->name == nxio->name)
rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$SB_IO_IN"));
+ if (ctx->nets.count(nxio->name)) {
+ int i = 0;
+ IdString new_name;
+ do {
+ new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
+ } while (ctx->nets.count(new_name));
+ rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name);
+ }
+
// Create a new top port net for accurate IO timing analysis and simulation netlists
if (ctx->ports.count(nxio->name)) {
IdString tn_netname = nxio->name;