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author	Miodrag Milanovic <mmicko@gmail.com>	2018-07-12 18:02:57 +0200
committer	Miodrag Milanovic <mmicko@gmail.com>	2018-07-12 18:03:10 +0200
commit	7b9b2bef3c622bd54225c1c44ee63a211e0e1d3e (patch)
tree	205e0473e3681c5d2a74a1d286c1d595db3580c5 /python/functions.py
parent	a8a3ba264704182547639053f71b0be0b31d05af (diff)
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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2021  Marcelina Kościelnicka <mwk@0x04.net>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "memlib.h"

#include <ctype.h>

#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/mem.h"
#include "kernel/qcsat.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

using namespace MemLibrary;

#define FACTOR_MUX 0.5
#define FACTOR_DEMUX 0.5
#define FACTOR_EMU 2

struct PassOptions {
	bool no_auto_distributed;
	bool no_auto_block;
	bool no_auto_huge;
	double logic_cost_rom;
	double logic_cost_ram;
};

struct WrPortConfig {
	// Index of the read port this port is merged with, or -1 if none.
	int rd_port;
	// Index of the PortGroup in the Ram.
	int port_group;
	int port_variant;
	const PortVariant *def;
	// Emulate priority logic for this list of (source) write port indices.
	std::vector<int> emu_prio;
	// If true, this port needs to end up with uniform byte enables to work correctly.
	bool force_uniform;

	WrPortConfig() : rd_port(-1), force_uniform(false) {}
};

struct RdPortConfig {
	// Index of the write port this port is merged with, or -1 if none.
	int wr_port;
	// Index of the PortGroup in the Ram.
	int port_group;
	int port_variant;
	const PortVariant *def;
	// If true, this is a sync port mapped into async mem, make an output
	// register.  Mutually exclusive with the following options.
	bool emu_sync;
	// Emulate the EN / ARST / SRST / init value circuitry.
	bool emu_en;
	bool emu_arst;
	bool emu_srst;
	bool emu_init;
	// Emulate EN-SRST priority.
	bool emu_srst_en_prio;
	// If true, use clk_en as rd_en.
	bool rd_en_to_clk_en;
	// Emulate transparency logic for this list of (source) write port indices.
	std::vector<int> emu_trans;

	RdPortConfig() : wr_port(-1), emu_sync(false), emu_en(false), emu_arst(false), emu_srst(false), emu_init(false), emu_srst_en_prio(false), rd_en_to_clk_en(false) {}
};

// The named clock and clock polarity assignments.
struct SharedClockConfig {
	bool used;
	SigBit clk;
	// For anyedge clocks.
	bool polarity;
	// For non-anyedge clocks.
	bool invert;
};

struct MemConfig {
	// Reference to the library ram definition
	const Ram *def;
	// Port assignments, indexed by Mem port index.
	std::vector<WrPortConfig> wr_ports;
	std::vector<RdPortConfig> rd_ports;
	std::vector<SharedClockConfig> shared_clocks;
	// Emulate read-first write-read behavior using soft logic.
	bool emu_read_first;
	// This many low bits of (target) address are always-0 on all ports.
	int base_width_log2;
	int unit_width_log2;
	std::vector<int> swizzle;
	int hard_wide_mask;
	int emu_wide_mask;
	// How many times the base memory block will need to be duplicated to get more
	// data bits.
	int repl_d;
	// How many times the whole memory array will need to be duplicated to cover
	// all read ports required.
	int repl_port;
	// Emulation score — how much circuitry we need to add for priority / transparency /
	// reset / initial value emulation.
	int score_emu;
	// Mux score — how much circuitry we need to add to manually decode whatever address
	// bits are not decoded by the memory array itself, for reads.
	int score_mux;
	// Demux score — how much circuitry we need to add to manually decode whatever address
	// bits are not decoded by the memory array itself, for writes.
	int score_demux;
	double cost;
	MemConfig() : emu_read_first(false) {}
};

typedef std::vector<MemConfig> MemConfigs;

struct MapWorker {
	Module *module;
	ModWalker modwalker;
	SigMap sigmap;
	SigMap sigmap_xmux;
	FfInitVals initvals;

	MapWorker(Module *module) : module(module), modwalker(module->design, module), sigmap(module), sigmap_xmux(module), initvals(&sigmap, module) {
		for (auto cell : module->cells())
		{
			if (cell->type == ID($mux))
			{
				RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
				RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));

				if (sig_a.is_fully_undef())
					sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
				else if (sig_b.is_fully_undef())
					sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
			}
		}
	}
};

struct SwizzleBit {
	bool valid;
	int mux_idx;
	int addr;
	int bit;
};

struct Swizzle {
	int addr_shift;
	int addr_start;
	int addr_end;
	std::vector<int> addr_mux_bits;
	std::vector<std::vector<SwizzleBit>> bits;
};

struct MemMapping {
	MapWorker &worker;
	QuickConeSat qcsat;
	Mem &mem;
	const Library &lib;
	const PassOptions &opts;
	std::vector<MemConfig> cfgs;
	bool logic_ok;
	double logic_cost;
	RamKind kind;
	std::string style;
	dict<int, int> wr_en_cache;
	dict<std::pair<int, int>, bool> wr_implies_rd_cache;
	dict<std::pair<int, int>, bool> wr_excludes_rd_cache;
	dict<std::pair<int, int>, bool> wr_excludes_srst_cache;

	MemMapping(MapWorker &worker, Mem &mem, const Library &lib, const PassOptions &opts) : worker(worker), qcsat(worker.modwalker), mem(mem), lib(lib), opts(opts) {
		determine_style();
		logic_ok = determine_logic_ok();
		if (GetSize(mem.wr_ports) == 0)
			logic_cost = mem.width * mem.size * opts.logic_cost_rom;
		else
			logic_cost = mem.width * mem.size * opts.logic_cost_ram;
		if (kind == RamKind::Logic)
			return;
		for (int i = 0; i < GetSize(lib.rams); i++) {
			auto &rdef = lib.rams[i];
			if (!check_ram_kind(rdef))
				continue;
			if (!check_ram_style(rdef))
				continue;
			if (!check_init(rdef))
				continue;
			if (rdef.prune_rom && mem.wr_ports.empty())
				continue;
			MemConfig cfg;
			cfg.def = &rdef;
			for (auto &cdef: rdef.shared_clocks) {
				(void)cdef;
				SharedClockConfig clk;
				clk.used = false;
				cfg.shared_clocks.push_back(clk);
			}
			cfgs.push_back(cfg);
		}
		assign_wr_ports();
		assign_rd_ports();
		handle_trans();
		// If we got this far, the memory is mappable.  The following two can require emulating
		// some functionality, but cannot cause the mapping to fail.
		handle_priority();
		handle_rd_rst();
		score_emu_ports();
		// Now it is just a matter of picking geometry.
		handle_geom();
		dump_configs(0);
		prune_post_geom();
		dump_configs(1);
	}

	bool addr_compatible(int wpidx, int rpidx) {
		auto &wport = mem.wr_ports[wpidx];
		auto &rport = mem.rd_ports[rpidx];
		int max_wide_log2 = std::max(rport.wide_log2, wport.wide_log2);
		SigSpec raddr = rport.addr.extract_end(max_wide_log2);
		SigSpec waddr = wport.addr.extract_end(max_wide_log2);
		int abits = std::max(GetSize(raddr), GetSize(waddr));
		raddr.extend_u0(abits);
		waddr.extend_u0(abits);
		return worker.sigmap_xmux(raddr) == worker.sigmap_xmux(waddr);
	}

	int get_wr_en(int wpidx) {
		auto it = wr_en_cache.find(wpidx);
		if (it != wr_en_cache.end())
			return it->second;
		int res = qcsat.ez->expression(qcsat.ez->OpOr, qcsat.importSig(mem.wr_ports[wpidx].en));
		wr_en_cache.insert({wpidx, res});
		return res;
	}

	bool get_wr_implies_rd(int wpidx, int rpidx) {
		auto key = std::make_pair(wpidx, rpidx);
		auto it = wr_implies_rd_cache.find(key);
		if (it != wr_implies_rd_cache.end())
			return it->second;
		int wr_en = get_wr_en(wpidx);
		int rd_en = qcsat.importSigBit(mem.rd_ports[rpidx].en[0]);
		qcsat.prepare();
		bool res = !qcsat.ez->solve(wr_en, qcsat.ez->NOT(rd_en));
		wr_implies_rd_cache.insert({key, res});
		return res;
	}

	bool get_wr_excludes_rd(int wpidx, int rpidx) {
		auto key = std::make_pair(wpidx, rpidx);
		auto it = wr_excludes_rd_cache.find(key);
		if (it != wr_excludes_rd_cache.end())
			return it->second;
		int wr_en = get_wr_en(wpidx);
		int rd_en = qcsat.importSigBit(mem.rd_ports[rpidx].en[0]);
		qcsat.prepare();
		bool res = !qcsat.ez->solve(wr_en, rd_en);
		wr_excludes_rd_cache.insert({key, res});
		return res;
	}

	bool get_wr_excludes_srst(int wpidx, int rpidx) {
		auto key = std::make_pair(wpidx, rpidx);
		auto it = wr_excludes_srst_cache.find(key);
		if (it != wr_excludes_srst_cache.end())
			return it->second;
		int wr_en = get_wr_en(wpidx);
		int srst = qcsat.importSigBit(mem.rd_ports[rpidx].srst);
		if (mem.rd_ports[rpidx].ce_over_srst) {
			int rd_en = qcsat.importSigBit(mem.rd_ports[rpidx].en[0]);
			srst = qcsat.ez->AND(srst, rd_en);
		}
		qcsat.prepare();
		bool res = !qcsat.ez->solve(wr_en, srst);
		wr_excludes_srst_cache.insert({key, res});
		return res;
	}

	void dump_configs(int stage);
	void dump_config(MemConfig &cfg);
	void determine_style();
	bool determine_logic_ok();
	bool check_ram_kind(const Ram &ram);
	bool check_ram_style(const Ram &ram);
	bool check_init(const Ram &ram);
	void assign_wr_ports();
	void assign_rd_ports();
	void handle_trans();
	void handle_priority();
	void handle_rd_rst();
	void score_emu_ports();
	void handle_geom();
	void prune_post_geom();
	void emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, const PortVariant &pdef, const char *name, int wpidx, int rpidx, const std::vector<int> &hw_addr_swizzle);
	void emit(const MemConfig &cfg);
};

void MemMapping::dump_configs(int stage) {
	const char *stage_name;
	switch (stage) {
		case 0:
			stage_name = "post-geometry";
			break;
		case 1:
			stage_name = "after post-geometry prune";
			break;
		default:
			abort();
	}
	log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module->name), log_id(mem.memid), stage_name);
	if (logic_ok) {
		log_debug("- logic fallback\n");
		log_debug("  - cost: %f\n", logic_cost);
	}
	for (auto &cfg: cfgs) {
		dump_config(cfg);
	}
}

void MemMapping::dump_config(MemConfig &cfg) {
	log_debug("- %s:\n", log_id(cfg.def->id));
	for (auto &it: cfg.def->options)
		log_debug("  - option %s %s\n", it.first.c_str(), log_const(it.second));
	log_debug("  - emulation score: %d\n", cfg.score_emu);
	log_debug("  - replicates (for ports): %d\n", cfg.repl_port);
	log_debug("  - replicates (for data): %d\n", cfg.repl_d);
	log_debug("  - mux score: %d\n", cfg.score_mux);
	log_debug("  - demux score: %d\n", cfg.score_demux);
	log_debug("  - cost: %f\n", cfg.cost);
	std::stringstream os;
	for (int x: cfg.def->dbits)
		os << " " << x;
	std::string dbits_s = os.str();
	log_debug("  - abits %d dbits%s\n", cfg.def->abits, dbits_s.c_str());
	if (cfg.def->byte != 0)
		log_debug("  - byte width %d\n", cfg.def->byte);
	log_debug("  - chosen base width %d\n", cfg.def->dbits[cfg.base_width_log2]);
	os.str("");
	for (int x: cfg.swizzle)
		if (x == -1)
			os << " -";
		else
			os << " " << x;
	std::string swizzle_s = os.str();
	log_debug("  - swizzle%s\n", swizzle_s.c_str());
	os.str("");
	for (int i = 0; (1 << i) <= cfg.hard_wide_mask; i++)
		if (cfg.hard_wide_mask & 1 << i)
			os << " " << i;
	std::string wide_s = os.str();
	if (cfg.hard_wide_mask)
		log_debug("  - hard wide bits%s\n", wide_s.c_str());
	if (cfg.emu_read_first)
		log_debug("  - emulate read-first behavior\n");
	for (int i = 0; i < GetSize(mem.wr_ports); i++) {
		auto &pcfg = cfg.wr_ports[i];
		if (pcfg.rd_port == -1)
			log_debug("  - write port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str());
		else
			log_debug("  - write port %d: port group %s (shared with read port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str(), pcfg.rd_port);

		for (auto &it: pcfg.def->options)
			log_debug("    - option %s %s\n", it.first.c_str(), log_const(it.second));
		if (cfg.def->width_mode == WidthMode::PerPort) {
			std::stringstream os;
			for (int i = pcfg.def->min_wr_wide_log2; i <= pcfg.def->max_wr_wide_log2; i++)
				os << " " << cfg.def->dbits[i];
			std::string widths_s = os.str();
			const char *note = "";
			if (pcfg.rd_port != -1)
				note = pcfg.def->width_tied ? " (tied)" : " (independent)";
			log_debug("    - widths%s%s\n", widths_s.c_str(), note);
		}
		for (auto i: pcfg.emu_prio)
			log_debug("    - emulate priority over write port %d\n", i);
	}
	for (int i = 0; i < GetSize(mem.rd_ports); i++) {
		auto &pcfg = cfg.rd_ports[i];
		if (pcfg.wr_port == -1)
			log_debug("  - read port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str());
		else
			log_debug("  - read port %d: port group %s (shared with write port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str(), pcfg.wr_port);
		for (auto &it: pcfg.def->options)
			log_debug("    - option %s %s\n", it.first.c_str(), log_const(it.second));
		if (cfg.def->width_mode == WidthMode::PerPort) {
			std::stringstream os;
			for (int i = pcfg.def->min_rd_wide_log2; i <= pcfg.def->max_rd_wide_log2; i++)
				os << " " << cfg.def->dbits[i];
			std::string widths_s = os.str();
			const char *note = "";
			if (pcfg.wr_port != -1)
				note = pcfg.def->width_tied ? " (tied)" : " (independent)";
			log_debug("    - widths%s%s\n", widths_s.c_str(), note);
		}
		if (pcfg.emu_sync)
			log_debug("    - emulate data register\n");
		if (pcfg.emu_en)
			log_debug("    - emulate clock enable\n");
		if (pcfg.emu_arst)
			log_debug("    - emulate async reset\n");
		if (pcfg.emu_srst)
			log_debug("    - emulate sync reset\n");
		if (pcfg.emu_init)
			log_debug("    - emulate init value\n");
		if (pcfg.emu_srst_en_prio)
			log_debug("    - emulate sync reset / enable priority\n");
		for (auto i: pcfg.emu_trans)
			log_debug("    - emulate transparency with write port %d\n", i);
	}
}

// Go through memory attributes to determine user-requested mapping style.
void MemMapping::determine_style() {
	kind = RamKind::Auto;
	style = "";
	if (mem.get_bool_attribute(ID::lram)) {
		kind = RamKind::Huge;
		return;
	}
	for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) {
		if (mem.has_attribute(attr)) {
			Const val = mem.attributes.at(attr);
			if (val == 1) {
				kind = RamKind::NotLogic;
				return;
			}
			std::string val_s = val.decode_string();
			for (auto &c: val_s)
				c = std::tolower(c);
			// Handled in memory_dff.
			if (val_s == "no_rw_check")
				continue;
			if (val_s == "auto") {
				// Nothing.
			} else if (val_s == "logic" || val_s == "registers") {
				kind = RamKind::Logic;
			} else if (val_s == "distributed") {
				kind = RamKind::Distributed;
			} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
				kind = RamKind::Block;
			} else if (val_s == "huge" || val_s == "ultra") {
				kind = RamKind::Huge;
			} else {
				kind = RamKind::NotLogic;
				style = val_s;
			}
			return;
		}
	}
	if (mem.get_bool_attribute(ID::logic_block))
		kind = RamKind::Logic;
}

// Determine whether the memory can be mapped entirely to soft logic.
bool MemMapping::determine_logic_ok() {
	if (kind != RamKind::Auto && kind != RamKind::Logic)
		return false;
	// Memory is mappable entirely to soft logic iff all its write ports are in the same clock domain.
	if (mem.wr_ports.empty())
		return true;
	for (auto &port: mem.wr_ports) {
		if (!port.clk_enable)
			return false;
		if (port.clk != mem.wr_ports[0].clk)
			return false;
		if (port.clk_polarity != mem.wr_ports[0].clk_polarity)
			return false;
	}
	return true;
}

// Apply RAM kind restrictions (logic/distributed/block/huge), if any.
bool MemMapping::check_ram_kind(const Ram &ram) {
	if (style != "")
		return true;
	if (ram.kind == kind)
		return true;
	if (kind == RamKind::Auto || kind == RamKind::NotLogic) {
		if (ram.kind == RamKind::Distributed && opts.no_auto_distributed)
			return false;
		if (ram.kind == RamKind::Block && opts.no_auto_block)
			return false;
		if (ram.kind == RamKind::Huge && opts.no_auto_huge)
			return false;
		return true;
	}
	return false;
}

// Apply specific RAM style restrictions, if any.
bool MemMapping::check_ram_style(const Ram &ram) {
	if (style == "")
		return true;
	for (auto &s: ram.style)
		if (s == style)
			return true;
	return false;
}

// Handle memory initializer restrictions, if any.
bool MemMapping::check_init(const Ram &ram) {
	bool has_nonx = false;
	bool has_one = false;

	for (auto &init: mem.inits) {
		if (init.data.is_fully_undef())
			continue;
		has_nonx = true;
		for (auto bit: init.data)
			if (bit == State::S1)
				has_one = true;
	}

	switch (ram.init) {
		case MemoryInitKind::None:
			return !has_nonx;
		case MemoryInitKind::Zero:
			return !has_one;
		default:
			return true;
	}
}

bool apply_clock(MemConfig &cfg, const PortVariant &def, SigBit clk, bool clk_polarity) {
	if (def.clk_shared == -1)
		return true;
	auto &cdef = cfg.def->shared_clocks[def.clk_shared];
	auto &ccfg = cfg.shared_clocks[def.clk_shared];
	if (cdef.anyedge) {
		if (!ccfg.used) {
			ccfg.used = true;
			ccfg.clk = clk;
			ccfg.polarity = clk_polarity;
			return true;
		} else {
			return ccfg.clk == clk && ccfg.polarity == clk_polarity;
		}
	} else {
		bool invert = clk_polarity ^ (def.clk_pol == ClkPolKind::Posedge);
		if (!ccfg.used) {
			ccfg.used = true;
			ccfg.clk = clk;
			ccfg.invert = invert;
			return true;
		} else {
			return ccfg.clk == clk && ccfg.invert == invert;
		}
	}
}

// Perform write port assignment, validating clock options as we go.
void MemMapping::assign_wr_ports() {
	for (auto &port: mem.wr_ports) {
		if (!port.clk_enable) {
			// Async write ports not supported.
			cfgs.clear();
			return;
		}
		MemConfigs new_cfgs;
		for (auto &cfg: cfgs) {
			for (int pgi = 0; pgi < GetSize(cfg.def->port_groups); pgi++) {
				auto &pg = cfg.def->port_groups[pgi];
				// Make sure the target port group still has a free port.
				int used = 0;
				for (auto &oport: cfg.wr_ports)
					if (oport.port_group == pgi)
						used++;
				if (used >= GetSize(pg.names))
					continue;
				for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) {
					auto &def = pg.variants[pvi];
					// Make sure the target is a write port.
					if (def.kind == PortKind::Ar || def.kind == PortKind::Sr)
						continue;
					MemConfig new_cfg = cfg;
					WrPortConfig pcfg;
					pcfg.rd_port = -1;
					pcfg.port_group = pgi;
					pcfg.port_variant = pvi;
					pcfg.def = &def;
					if (!apply_clock(new_cfg, def, port.clk, port.clk_polarity))
						continue;
					new_cfg.wr_ports.push_back(pcfg);
					new_cfgs.push_back(new_cfg);
				}
			}
		}
		cfgs = new_cfgs;
	}
}

// Perform read port assignment, validating clock and rden options as we go.
void MemMapping::assign_rd_ports() {
	for (int pidx = 0; pidx < GetSize(mem.rd_ports); pidx++) {
		auto &port = mem.rd_ports[pidx];
		MemConfigs new_cfgs;
		for (auto &cfg: cfgs) {
			// First pass: read port not shared with a write port.
			for (int pgi = 0; pgi < GetSize(cfg.def->port_groups); pgi++) {
				auto &pg = cfg.def->port_groups[pgi];
				// Make sure the target port group has a port not used up by write ports.
				// Overuse by other read ports is not a problem — this will just result
				// in memory duplication.
				int used = 0;
				for (auto &oport: cfg.wr_ports)
					if (oport.port_group == pgi)
						used++;
				if (used >= GetSize(pg.names))
					continue;
				for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) {
					auto &def = pg.variants[pvi];
					// Make sure the target is a read port.
					if (def.kind == PortKind::Sw)
						continue;
					// If mapping an async port, accept only async defs.
					if (!port.clk_enable) {
						if (def.kind == PortKind::Sr || def.kind == PortKind::Srsw)
							continue;
					}
					MemConfig new_cfg = cfg;
					RdPortConfig pcfg;
					pcfg.wr_port = -1;
					pcfg.port_group = pgi;
					pcfg.port_variant = pvi;
					pcfg.def = &def;
					if (def.kind == PortKind::Sr || def.kind == PortKind::Srsw) {
						pcfg.emu_sync = false;
						if (!apply_clock(new_cfg, def, port.clk, port.clk_polarity))
							continue;
						// Decide if rden is usable.
						if (port.en != State::S1) {
							if (def.clk_en) {
								pcfg.rd_en_to_clk_en = true;
							} else {
								pcfg.emu_en = !def.rd_en;
							}
						}
					} else {
						pcfg.emu_sync = port.clk_enable;
					}
					new_cfg.rd_ports.push_back(pcfg);
					new_cfgs.push_back(new_cfg);
				}
			}
			// Second pass: read port shared with a write port.
			for (int wpidx = 0; wpidx < GetSize(mem.wr_ports); wpidx++) {
				auto &wport = mem.wr_ports[wpidx];
				auto &wpcfg = cfg.wr_ports[wpidx];
				auto &def = *wpcfg.def;
				// Make sure the write port is not yet shared.
				if (wpcfg.rd_port != -1)
					continue;
				// Make sure the target is a read port.
				if (def.kind == PortKind::Sw)
					continue;
				// Validate address compatibility.
				if (!addr_compatible(wpidx, pidx))
					continue;
				// Validate clock compatibility, if needed.
				if (def.kind == PortKind::Srsw) {
					if (!port.clk_enable)
						continue;
					if (port.clk != wport.clk)
						continue;
					if (port.clk_polarity != wport.clk_polarity)
						continue;
				}
				// Okay, let's fill it in.
				MemConfig new_cfg = cfg;
				new_cfg.wr_ports[wpidx].rd_port = pidx;
				RdPortConfig pcfg;
				pcfg.wr_port = wpidx;
				pcfg.port_group = wpcfg.port_group;
				pcfg.port_variant = wpcfg.port_variant;
				pcfg.def = wpcfg.def;
				pcfg.emu_sync = port.clk_enable && def.kind == PortKind::Arsw;
				// For srsw, check rden capability.
				if (def.kind == PortKind::Srsw) {
					bool trans = port.transparency_mask[wpidx];
					bool col_x = port.collision_x_mask[wpidx];
					if (def.rdwr == RdWrKind::NoChange) {
						if (!get_wr_excludes_rd(wpidx, pidx)) {
							if (!trans && !col_x)
								continue;
							if (trans)
								pcfg.emu_trans.push_back(wpidx);
							new_cfg.wr_ports[wpidx].force_uniform = true;
						}
						if (port.en != State::S1) {
							if (def.clk_en) {
								pcfg.rd_en_to_clk_en = true;
							} else {
								pcfg.emu_en = !def.rd_en;
							}
						}
					} else {
						if (!col_x && !trans && def.rdwr != RdWrKind::Old)
							continue;
						if (trans) {
							if (def.rdwr != RdWrKind::New && def.rdwr != RdWrKind::NewOnly)
								pcfg.emu_trans.push_back(wpidx);
						}
						if (def.rdwr == RdWrKind::NewOnly) {
							if (!get_wr_excludes_rd(wpidx, pidx))
								new_cfg.wr_ports[wpidx].force_uniform = true;
						}
						if (port.en != State::S1) {
							if (def.clk_en) {
								if (get_wr_implies_rd(wpidx, pidx)) {
									pcfg.rd_en_to_clk_en = true;
								} else {
									pcfg.emu_en = !def.rd_en;
								}
							} else {
								pcfg.emu_en = !def.rd_en;
							}
						}
					}
				}
				new_cfg.rd_ports.push_back(pcfg);
				new_cfgs.push_back(new_cfg);
			}
		}
		cfgs = new_cfgs;
	}
}

// Validate transparency restrictions, determine where to add soft transparency logic.
void MemMapping::handle_trans() {
	if (mem.emulate_read_first_ok()) {
		MemConfigs new_cfgs;
		for (auto &cfg: cfgs) {
			new_cfgs.push_back(cfg);
			bool ok = true;
			// Using this trick will break read-write port sharing.
			for (auto &pcfg: cfg.rd_ports)
				if (pcfg.wr_port != -1)
					ok = false;
			if (ok) {
				cfg.emu_read_first = true;
				new_cfgs.push_back(cfg);
			}
		}
		cfgs = new_cfgs;
	}
	for (int rpidx = 0; rpidx < GetSize(mem.rd_ports); rpidx++) {
		auto &rport = mem.rd_ports[rpidx];
		if (!rport.clk_enable)
			continue;
		for (int wpidx = 0; wpidx < GetSize(mem.wr_ports); wpidx++) {
			auto &wport = mem.wr_ports[wpidx];
			if (!wport.clk_enable)
				continue;
			if (rport.clk != wport.clk)
				continue;
			if (rport.clk_polarity != wport.clk_polarity)
				continue;
			// If we got this far, we have a transparency restriction
			// to uphold.
			MemConfigs new_cfgs;
			for (auto &cfg: cfgs) {
				auto &rpcfg = cfg.rd_ports[rpidx];
				auto &wpcfg = cfg.wr_ports[wpidx];
				// The transparency relation for shared ports already handled while assigning them.
				if (rpcfg.wr_port == wpidx) {
					new_cfgs.push_back(cfg);
					continue;
				}
				if (rport.collision_x_mask[wpidx] && !cfg.emu_read_first) {
					new_cfgs.push_back(cfg);
					continue;
				}
				bool transparent = rport.transparency_mask[wpidx] || cfg.emu_read_first;
				if (rpcfg.emu_sync) {
					// For async read port, just add the transparency logic
					// if necessary.
					if (transparent)
						rpcfg.emu_trans.push_back(wpidx);
					new_cfgs.push_back(cfg);
				} else {
					// Otherwise, split through the relevant wrtrans caps.
					// For non-transparent ports, the cap needs to be present.
					// For transparent ports, we can emulate transparency
					// even without a direct cap.
					bool found = false;
					for (auto &tdef: wpcfg.def->wrtrans) {
						// Check if the target matches.
						if (tdef.target_kind == WrTransTargetKind::Group && rpcfg.port_group != tdef.target_group)
							continue;
						// Check if the transparency kind is acceptable.
						if (transparent) {
							if (tdef.kind == WrTransKind::Old)
								continue;
						} else {
							if (tdef.kind != WrTransKind::Old)
								continue;
						}
						// Okay, we can use this cap.
						new_cfgs.push_back(cfg);
						found = true;
						break;
					}
					if (!found && transparent) {
						// If the port pair is transparent, but no cap was
						// found, use emulation.
						rpcfg.emu_trans.push_back(wpidx);
						new_cfgs.push_back(cfg);
					}
				}
			}
			cfgs = new_cfgs;
		}
	}
}

// Determine where to add soft priority logic.
void MemMapping::handle_priority() {
	for (int p1idx = 0; p1idx < GetSize(mem.wr_ports); p1idx++) {
		for (int p2idx = 0; p2idx < GetSize(mem.wr_ports); p2idx++) {
			auto &port2 = mem.wr_ports[p2idx];
			if (!port2.priority_mask[p1idx])
				continue;
			for (auto &cfg: cfgs) {
				auto &p1cfg = cfg.wr_ports[p1idx];
				auto &p2cfg = cfg.wr_ports[p2idx];
				bool found = false;
				for (auto &pgi: p2cfg.def->wrprio) {
					if (pgi == p1cfg.port_group) {
						found = true;
						break;
					}
				}
				// If no cap was found, emulate.
				if (!found)
					p2cfg.emu_prio.push_back(p1idx);
			}
		}
	}
}

bool is_all_zero(const Const &val) {
	for (auto bit: val.bits)
		if (bit == State::S1)
			return false;
	return true;
}

// Determine where to add soft init value / reset logic.
void MemMapping::handle_rd_rst() {
	for (auto &cfg: cfgs) {
		for (int pidx = 0; pidx < GetSize(mem.rd_ports); pidx++) {
			auto &port = mem.rd_ports[pidx];
			auto &pcfg = cfg.rd_ports[pidx];
			// Only sync ports are relevant.
			// If emulated by async port or we already emulate CE, init will be
			// included for free.
			if (!port.clk_enable || pcfg.emu_sync || pcfg.emu_en)
				continue;
			switch (pcfg.def->rdinitval) {
				case ResetValKind::None:
					pcfg.emu_init = !port.init_value.is_fully_undef();
					break;
				case ResetValKind::Zero:
					pcfg.emu_init = !is_all_zero(port.init_value);
					break;
				default:
					break;
			}
			Const init_val = port.init_value;
			if (port.arst != State::S0) {
				switch (pcfg.def->rdarstval) {
					case ResetValKind::None:
						pcfg.emu_arst = true;
						break;
					case ResetValKind::Zero:
						pcfg.emu_arst = !is_all_zero(port.arst_value);
						break;
					case ResetValKind::Init:
						if (init_val.is_fully_undef())
							init_val = port.arst_value;
						pcfg.emu_arst = init_val != port.arst_value;
						break;
					default:
						break;
				}
			}
			if (port.srst != State::S0) {
				switch (pcfg.def->rdsrstval) {
					case ResetValKind::None:
						pcfg.emu_srst = true;
						break;
					case ResetValKind::Zero:
						pcfg.emu_srst = !is_all_zero(port.srst_value);
						break;
					case ResetValKind::Init:
						if (init_val.is_fully_undef())
							init_val = port.srst_value;
						pcfg.emu_srst = init_val != port.srst_value;
						break;
					default:
						break;
				}
				if (!pcfg.emu_srst && pcfg.def->rdsrst_block_wr && pcfg.wr_port != -1) {
					if (!get_wr_excludes_srst(pcfg.wr_port, pidx))
						pcfg.emu_srst = true;
				}
				if (!pcfg.emu_srst && port.en != State::S1) {
					if (port.ce_over_srst) {
						switch (pcfg.def->rdsrstmode) {
							case SrstKind::Ungated:
								pcfg.emu_srst_en_prio = true;
								break;
							case SrstKind::GatedClkEn:
								pcfg.emu_srst_en_prio = !pcfg.rd_en_to_clk_en;
								break;
							case SrstKind::GatedRdEn:
								break;
							default:
								log_assert(0);
						}
					} else {
						switch (pcfg.def->rdsrstmode) {
							case SrstKind::Ungated:
								break;
							case SrstKind::GatedClkEn:
								if (pcfg.rd_en_to_clk_en) {
									if (pcfg.def->rd_en) {
										pcfg.rd_en_to_clk_en = false;
									} else {
										pcfg.emu_srst_en_prio = true;
									}
								}
								break;
							case SrstKind::GatedRdEn:
								pcfg.emu_srst_en_prio = true;
								break;
							default:
								log_assert(0);
						}
					}
				}
			} else {
				if (pcfg.def->rd_en && pcfg.def->rdwr == RdWrKind::NoChange && pcfg.wr_port != -1) {
					pcfg.rd_en_to_clk_en = false;
				}
			}
		}
	}
}

void MemMapping::score_emu_ports() {
	for (auto &cfg: cfgs) {
		std::vector<int> port_usage_wr(cfg.def->port_groups.size());
		std::vector<int> port_usage_rd(cfg.def->port_groups.size());
		int score = 0;
		// 3 points for every write port if we need to do read-first emulation.
		if (cfg.emu_read_first)
			score += 3 * GetSize(cfg.wr_ports);
		for (auto &pcfg: cfg.wr_ports) {
			// 1 point for every priority relation we need to fix up.
			// This is just a gate for every distinct wren pair.
			score += GetSize(pcfg.emu_prio);
			port_usage_wr[pcfg.port_group]++;
		}
		for (auto &pcfg: cfg.rd_ports) {
			// 3 points for every soft transparency logic instance.  This involves
			// registers and other major mess.
			score += 3 * GetSize(pcfg.emu_trans);
			// 3 points for CE soft logic.  Likewise involves registers.
			// If we already do this, subsumes any init/srst/arst emulation.
			if (pcfg.emu_en)
				score += 3;
			// 2 points for soft init value / reset logic: involves single bit
			// register and some muxes.
			if (pcfg.emu_init)
				score += 2;
			if (pcfg.emu_arst)
				score += 2;
			if (pcfg.emu_srst)
				score += 2;
			// 1 point for wrong srst/en priority (fixed with a single gate).
			if (pcfg.emu_srst_en_prio)
				score++;
			// 1 point for every non-shared read port used, as a tiebreaker
			// to prefer single-port configs.
			if (pcfg.wr_port == -1) {
				score++;
				port_usage_rd[pcfg.port_group]++;
			}
		}
		cfg.score_emu = score;
		int repl_port = 1;
		for (int i = 0; i < GetSize(cfg.def->port_groups); i++) {
			int space = GetSize(cfg.def->port_groups[i].names) - port_usage_wr[i];
			log_assert(space >= 0);
			if (port_usage_rd[i] > 0) {
				log_assert(space > 0);
				int usage = port_usage_rd[i];
				int cur = (usage + space - 1) / space;
				if (cur > repl_port)
					repl_port = cur;
			}
		}
		cfg.repl_port = repl_port;
	}
}

void MemMapping::handle_geom() {
	std::vector<int> wren_size;
	for (auto &port: mem.wr_ports) {
		SigSpec en = port.en;
		en.sort_and_unify();
		wren_size.push_back(GetSize(en));
	}
	for (auto &cfg: cfgs) {
		// First, create a set of "byte boundaries": the bit positions in source memory word
		// that have write enable different from the previous bit in any write port.
		// Bit 0 is considered to be a byte boundary as well.
		// Likewise, create a set of "word boundaries" that are like above, but only for write ports
		// with the "force uniform" flag set.
		std::vector<bool> byte_boundary(mem.width, false);
		std::vector<bool> word_boundary(mem.width, false);
		byte_boundary[0] = true;
		for (int pidx = 0; pidx < GetSize(mem.wr_ports); pidx++) {


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