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authorgatecat <gatecat@ds0.me>2021-03-08 15:05:58 +0000
committergatecat <gatecat@ds0.me>2021-03-08 15:59:18 +0000
commit08c7f97b1e2262588d96cbacfaf6e1e216b6035e (patch)
tree943b9516fc4ee2dc21da4a17b65ddbe9e22c2014 /nexus/fasm.cc
parent91064c7ec8b825732c2072fa8ab5cf8abb1662fe (diff)
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nexus: Support for hard DPHY
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'nexus/fasm.cc')
-rw-r--r--nexus/fasm.cc32
1 files changed, 32 insertions, 0 deletions
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 0b8b6377..4394aebc 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -569,6 +569,15 @@ struct NexusFasmWriter
{"SSC_STEP_IN", 7}, {"SSC_TBASE", 12},
{"V2I_PP_ICTRL", 5},
};
+
+ // Which MIPI params are 'word' values
+ const std::unordered_map<std::string, int> dphy_word_params = {
+ {"CM", 8}, {"CN", 5}, {"CO", 3}, {"RSEL", 2}, {"RXCDRP", 2},
+ {"RXDATAWIDTHHS", 2}, {"RXLPRP", 3}, {"TEST_ENBL", 6},
+ {"TEST_PATTERN", 32}, {"TST", 4}, {"TXDATAWIDTHHS", 2},
+ {"UC_PRG_RXHS_SETTLE", 6}, {"U_PRG_HS_PREPARE", 2},
+ {"U_PRG_HS_TRAIL", 6}, {"U_PRG_HS_ZERO", 6}, {"U_PRG_RXHS_SETTLE", 6}
+ };
/* clang-format on */
// Write out config for some kind of PLL cell
@@ -596,6 +605,27 @@ struct NexusFasmWriter
}
pop();
}
+ // Write out config for a DPHY_CORE cell
+ // TODO: duplication with PLL and other hard IP...
+ void write_dphy(const CellInfo *cell)
+ {
+ BelId bel = cell->bel;
+ push(stringf("IP_%s", ctx->nameOf(IdString(ctx->bel_data(bel).name))));
+ for (auto param : sorted_cref(cell->params)) {
+ const std::string &name = param.first.str(ctx);
+ if (is_mux_param(name) || name == "GSR")
+ continue;
+ auto fnd_word = dphy_word_params.find(name);
+ if (fnd_word != dphy_word_params.end()) {
+ write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
+ ctx->parse_lattice_param(cell, param.first, fnd_word->second, 0).as_int64(),
+ fnd_word->second);
+ } else {
+ write_bit(stringf("%s.%s", name.c_str(), param.second.as_string().c_str()));
+ }
+ }
+ pop();
+ }
// Write out config for an LRAM_CORE cell
void write_lram(const CellInfo *cell)
{
@@ -750,6 +780,8 @@ struct NexusFasmWriter
write_pll(ci);
else if (ci->type == id_LRAM_CORE)
write_lram(ci);
+ else if (ci->type == id_DPHY_CORE)
+ write_dphy(ci);
blank();
}
// Write config for unused bels