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| author | gatecat <gatecat@ds0.me> | 2021-12-12 14:59:34 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-12 14:59:34 +0000 |
| commit | cb362c2256fd18a4dc7ce624cbd4b027b56442b3 (patch) | |
| tree | d5200d40c937781f472578a48309331c5f0603f8 /mistral | |
| parent | 1c8d4d6460a24251c346f45e94e1d139ef3ac0eb (diff) | |
| parent | 61597e14a7fe488fcfc223d3109da1d30a2ec71b (diff) | |
| download | nextpnr-cb362c2256fd18a4dc7ce624cbd4b027b56442b3.tar.gz nextpnr-cb362c2256fd18a4dc7ce624cbd4b027b56442b3.tar.bz2 nextpnr-cb362c2256fd18a4dc7ce624cbd4b027b56442b3.zip | |
Merge pull request #869 from YosysHQ/gatecat/mistral-route-fix
mistral: DATAIN and DATAOUT of GPIO have swapped
Diffstat (limited to 'mistral')
| -rw-r--r-- | mistral/io.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mistral/io.cc b/mistral/io.cc index 3a72b001..dab3672e 100644 --- a/mistral/io.cc +++ b/mistral/io.cc @@ -31,9 +31,9 @@ void Arch::create_gpio(int x, int y) BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO); add_bel_pin(bel, id_PAD, PORT_INOUT, pad); // FIXME: is the port index of zero always correct? - add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0)); + add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)); add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0)); - add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)); + add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0)); bel_data(bel).block_index = z; } } |