Merge pull request #1010 from YosysHQ/gatecat/idf

refactor: id(stringf(...)) to new idf(...) helper

6 files changed, 43 insertions, 52 deletions

diff --git a/mistral/arch.cc b/mistral/arch.cc
index 46ed4f62..4023f5c3 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -88,7 +88,7 @@ Arch::Arch(ArchArgs args)
 
     // Setup fast identifier maps
     for (int i = 0; i < 1024; i++) {
-        IdString int_id = id(stringf("%d", i));
+        IdString int_id = idf("%d", i);
         int2id.push_back(int_id);
         id2int[int_id] = i;
     }
diff --git a/mistral/globals.cc b/mistral/globals.cc
index 1ba70919..6af8920d 100644
--- a/mistral/globals.cc
+++ b/mistral/globals.cc
@@ -30,7 +30,7 @@ void Arch::create_clkbuf(int x, int y)
             continue; // TODO: why do other Zs not work?
         // For now we only consider the input path from general routing, other inputs like dedicated clock pins are
         // still a TODO
-        BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA);
+        BelId bel = add_bel(x, y, idf("CLKBUF[%d]", z), id_MISTRAL_CLKENA);
         add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z));
         add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT));
         // TODO: enable pin
@@ -48,9 +48,9 @@ void Arch::create_hps_mpu_general_purpose(int x, int y)
     BelId gp_bel =
             add_bel(x, y, id_cyclonev_hps_interface_mpu_general_purpose, id_cyclonev_hps_interface_mpu_general_purpose);
     for (int i = 0; i < 32; i++) {
-        add_bel_pin(gp_bel, id(stringf("gp_in[%d]", i)), PORT_IN,
+        add_bel_pin(gp_bel, idf("gp_in[%d]", i), PORT_IN,
                     get_port(CycloneV::HPS_MPU_GENERAL_PURPOSE, x, y, -1, CycloneV::GP_IN, i));
-        add_bel_pin(gp_bel, id(stringf("gp_out[%d]", i)), PORT_OUT,
+        add_bel_pin(gp_bel, idf("gp_out[%d]", i), PORT_OUT,
                     get_port(CycloneV::HPS_MPU_GENERAL_PURPOSE, x, y, -1, CycloneV::GP_OUT, i));
     }
 }
diff --git a/mistral/io.cc b/mistral/io.cc
index c8d0238d..6690fc16 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -27,8 +27,8 @@ void Arch::create_gpio(int x, int y)
 {
     for (int z = 0; z < 4; z++) {
         // Notional pad wire
-        WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
-        BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
+        WireId pad = add_wire(x, y, idf("PAD[%d]", z));
+        BelId bel = add_bel(x, y, idf("IO[%d]", z), id_MISTRAL_IO);
         add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
         if (has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
             // FIXME: is the port index of zero always correct?
diff --git a/mistral/lab.cc b/mistral/lab.cc
index 4b66ed0c..d65ccf53 100644
--- a/mistral/lab.cc
+++ b/mistral/lab.cc
@@ -37,10 +37,10 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
     // Create the control set and E/F selection - which is per pair of FF
     for (int i = 0; i < 2; i++) {
         // Wires
-        alm.sel_clk[i] = arch->add_wire(x, y, arch->id(stringf("CLK%c[%d]", i ? 'B' : 'T', z)));
-        alm.sel_ena[i] = arch->add_wire(x, y, arch->id(stringf("ENA%c[%d]", i ? 'B' : 'T', z)));
-        alm.sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z)));
-        alm.sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z)));
+        alm.sel_clk[i] = arch->add_wire(x, y, arch->idf("CLK%c[%d]", i ? 'B' : 'T', z));
+        alm.sel_ena[i] = arch->add_wire(x, y, arch->idf("ENA%c[%d]", i ? 'B' : 'T', z));
+        alm.sel_aclr[i] = arch->add_wire(x, y, arch->idf("ACLR%c[%d]", i ? 'B' : 'T', z));
+        alm.sel_ef[i] = arch->add_wire(x, y, arch->idf("%cEF[%d]", i ? 'B' : 'T', z));
         // Muxes - three CLK/ENA per LAB, two ACLR
         for (int j = 0; j < 3; j++) {
             arch->add_pip(lab.clk_wires[j], alm.sel_clk[i]);
@@ -72,20 +72,20 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
             }
         } else {
             // Output from last combinational unit
-            carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1)));
-            share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1)));
+            carry_in = arch->add_wire(x, y, arch->idf("CARRY[%d]", (z * 2 + i) - 1));
+            share_in = arch->add_wire(x, y, arch->idf("SHARE[%d]", (z * 2 + i) - 1));
         }
 
         if (z == 9 && i == 1) {
             carry_out = arch->add_wire(x, y, id_CO);
             share_out = arch->add_wire(x, y, id_SHAREOUT);
         } else {
-            carry_out = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", z * 2 + i)));
-            share_out = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", z * 2 + i)));
+            carry_out = arch->add_wire(x, y, arch->idf("CARRY[%d]", z * 2 + i));
+            share_out = arch->add_wire(x, y, arch->idf("SHARE[%d]", z * 2 + i));
         }
 
-        BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_COMB%d", z, i)),
-                                  lab.is_mlab ? id_MISTRAL_MCOMB : id_MISTRAL_COMB);
+        BelId bel =
+                arch->add_bel(x, y, arch->idf("ALM%d_COMB%d", z, i), lab.is_mlab ? id_MISTRAL_MCOMB : id_MISTRAL_COMB);
         // LUT/MUX inputs
         arch->add_bel_pin(bel, id_A, PORT_IN, arch->get_port(block_type, x, y, z, CycloneV::A));
         arch->add_bel_pin(bel, id_B, PORT_IN, arch->get_port(block_type, x, y, z, CycloneV::B));
@@ -101,7 +101,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
         arch->add_bel_pin(bel, id_CO, PORT_OUT, carry_out);
         arch->add_bel_pin(bel, id_SHAREOUT, PORT_OUT, share_out);
         // Combinational output
-        alm.comb_out[i] = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i)));
+        alm.comb_out[i] = arch->add_wire(x, y, arch->idf("COMBOUT[%d]", z * 2 + i));
         arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, alm.comb_out[i]);
         if (lab.is_mlab) {
             // Write address - shared between all ALMs in a LAB
@@ -128,11 +128,11 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
 
     for (int i = 0; i < 4; i++) {
         // FF input, selected by *PKREG*
-        alm.ff_in[i] = arch->add_wire(x, y, arch->id(stringf("FFIN[%d]", (z * 4) + i)));
+        alm.ff_in[i] = arch->add_wire(x, y, arch->idf("FFIN[%d]", (z * 4) + i));
         arch->add_pip(alm.comb_out[i / 2], alm.ff_in[i]);
         arch->add_pip(alm.sel_ef[i / 2], alm.ff_in[i]);
         // FF bel
-        BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_FF%d", z, i)), id_MISTRAL_FF);
+        BelId bel = arch->add_bel(x, y, arch->idf("ALM%d_FF%d", z, i), id_MISTRAL_FF);
         arch->add_bel_pin(bel, id_CLK, PORT_IN, alm.sel_clk[i / 2]);
         arch->add_bel_pin(bel, id_ENA, PORT_IN, alm.sel_ena[i / 2]);
         arch->add_bel_pin(bel, id_ACLR, PORT_IN, alm.sel_aclr[i / 2]);
@@ -142,7 +142,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
         arch->add_bel_pin(bel, id_SDATA, PORT_IN, alm.sel_ef[i / 2]);
 
         // FF output
-        alm.ff_out[i] = arch->add_wire(x, y, arch->id(stringf("FFOUT[%d]", (z * 4) + i)));
+        alm.ff_out[i] = arch->add_wire(x, y, arch->idf("FFOUT[%d]", (z * 4) + i));
         arch->add_bel_pin(bel, id_Q, PORT_OUT, alm.ff_out[i]);
         // Output mux (*DFF*)
         WireId out = arch->get_port(block_type, x, y, z, outputs[i]);
@@ -182,7 +182,7 @@ void Arch::create_lab(int x, int y, bool is_mlab)
     // Clocks - hardcode to CLKA choices, as both CLKA and CLKB coming from general routing causes unexpected
     // permutations
     for (int i = 0; i < 3; i++) {
-        lab.clk_wires[i] = add_wire(x, y, id(stringf("CLK%d", i)));
+        lab.clk_wires[i] = add_wire(x, y, idf("CLK%d", i));
         add_pip(get_port(block_type, x, y, -1, CycloneV::CLKIN, 0), lab.clk_wires[i]);  // dedicated routing
         add_pip(get_port(block_type, x, y, -1, CycloneV::DATAIN, 0), lab.clk_wires[i]); // general routing
     }
@@ -278,7 +278,7 @@ void Arch::assign_comb_info(CellInfo *cell) const
         cell->combInfo.lut_input_count = 5;
         cell->combInfo.lut_bits_count = 32;
         for (int i = 0; i < 5; i++)
-            cell->combInfo.lut_in[i] = cell->getPort(id(stringf("B1ADDR[%d]", i)));
+            cell->combInfo.lut_in[i] = cell->getPort(idf("B1ADDR[%d]", i));
         auto key = get_mlab_key(cell);
         cell->combInfo.mlab_group = mlab_groups(key);
         cell->combInfo.comb_out = cell->getPort(id_B1DATA);
@@ -797,8 +797,8 @@ static void assign_mlab_inputs(Context *ctx, CellInfo *cell, int lut)
 
     std::array<IdString, 6> raddr_pins{id_A, id_B, id_C, id_D, id_F0};
     for (int i = 0; i < 5; i++) {
-        cell->pin_data[ctx->id(stringf("A1ADDR[%d]", i))].bel_pins = {ctx->id(stringf("WA%d", i))};
-        cell->pin_data[ctx->id(stringf("B1ADDR[%d]", i))].bel_pins = {raddr_pins.at(i)};
+        cell->pin_data[ctx->idf("A1ADDR[%d]", i)].bel_pins = {ctx->idf("WA%d", i)};
+        cell->pin_data[ctx->idf("B1ADDR[%d]", i)].bel_pins = {raddr_pins.at(i)};
     }
 }
 
@@ -918,7 +918,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
             CellInfo *ff = ffs[i * 2 + j];
             if (!ff || !ff->ffInfo.datain || alm_data.l6_mode)
                 continue;
-            CellInfo *rt_lut = createCell(id(stringf("%s$ROUTETHRU", nameOf(ff))), id_MISTRAL_BUF);
+            CellInfo *rt_lut = createCell(idf("%s$ROUTETHRU", nameOf(ff)), id_MISTRAL_BUF);
             rt_lut->addInput(id_A);
             rt_lut->addOutput(id_Q);
             // Disconnect the original data input to the FF, and connect it to the route-thru LUT instead
diff --git a/mistral/m10k.cc b/mistral/m10k.cc
index 4da1204f..df44c663 100644
--- a/mistral/m10k.cc
+++ b/mistral/m10k.cc
@@ -27,34 +27,28 @@ void Arch::create_m10k(int x, int y)
     add_bel_pin(bel, id_ADDRSTALLA, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
     add_bel_pin(bel, id_ADDRSTALLB, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
     for (int z = 0; z < 2; z++) {
-        add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
+        add_bel_pin(bel, idf("BYTEENABLEA[%d]", z), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
-        add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
+        add_bel_pin(bel, idf("BYTEENABLEB[%d]", z), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
-        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
-        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
-        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z + 6)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6));
+        add_bel_pin(bel, idf("ACLR[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
+        add_bel_pin(bel, idf("RDEN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
+        add_bel_pin(bel, idf("WREN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
+        add_bel_pin(bel, idf("CLKIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
+        add_bel_pin(bel, idf("CLKIN[%d]", z + 6), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6));
     }
     for (int z = 0; z < 4; z++) {
-        add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
+        add_bel_pin(bel, idf("ENABLE[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
     }
     for (int z = 0; z < 12; z++) {
-        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
-        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
+        add_bel_pin(bel, idf("ADDRA[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
+        add_bel_pin(bel, idf("ADDRB[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
     }
     for (int z = 0; z < 20; z++) {
-        add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
-        add_bel_pin(bel, id(stringf("DATABIN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
-        add_bel_pin(bel, id(stringf("DATAAOUT[%d]", z)), PORT_OUT,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
-        add_bel_pin(bel, id(stringf("DATABOUT[%d]", z)), PORT_OUT,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
+        add_bel_pin(bel, idf("DATAAIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
+        add_bel_pin(bel, idf("DATABIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
+        add_bel_pin(bel, idf("DATAAOUT[%d]", z), PORT_OUT, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
+        add_bel_pin(bel, idf("DATABOUT[%d]", z), PORT_OUT, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
     }
 }
 
diff --git a/mistral/pack.cc b/mistral/pack.cc
index 27ad3c92..709479a2 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -417,10 +417,8 @@ struct MistralPacker
                 bit_offset = 1;
             }
             for (int bit = bit_offset; bit < abits; bit++) {
-                ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {
-                        ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
-                ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {
-                        ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
+                ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset)};
+                ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset)};
             }
 
             // Data lines
@@ -451,13 +449,12 @@ struct MistralPacker
             }
             for (int bit = 0; bit < dbits; bit++) {
                 for (int offset : offsets) {
-                    ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(
-                            ctx->id(stringf("DATAAIN[%d]", bit + offset)));
+                    ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATAAIN[%d]", bit + offset));
                 }
             }
 
             for (int bit = 0; bit < dbits; bit++) {
-                ci->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))};
+                ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit)};
             }
         }
     }