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| author | gatecat <gatecat@ds0.me> | 2021-10-03 19:33:07 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-10-05 12:40:47 +0100 |
| commit | f5f7ef68649e873e6e5dc912544ed8abb5eb8fc3 (patch) | |
| tree | d8a2c6f41f7c97b3ba56d73821a4d462ccce3842 /mistral/arch.h | |
| parent | fe31fba6231e31fa642f25e1ab23d588315e5510 (diff) | |
| download | nextpnr-f5f7ef68649e873e6e5dc912544ed8abb5eb8fc3.tar.gz nextpnr-f5f7ef68649e873e6e5dc912544ed8abb5eb8fc3.tar.bz2 nextpnr-f5f7ef68649e873e6e5dc912544ed8abb5eb8fc3.zip | |
mistral: Adding support for MLABs as memory
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral/arch.h')
| -rw-r--r-- | mistral/arch.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/mistral/arch.h b/mistral/arch.h index a808f69d..77a35caf 100644 --- a/mistral/arch.h +++ b/mistral/arch.h @@ -437,6 +437,7 @@ struct Arch : BaseArch<ArchRanges> bool isValidBelForCellType(IdString cell_type, BelId bel) const override; BelBucketId getBelBucketForCellType(IdString cell_type) const override; + BelBucketId getBelBucketForBel(BelId bel) const override; // ------------------------------------------------- @@ -469,6 +470,7 @@ struct Arch : BaseArch<ArchRanges> bool is_alm_legal(uint32_t lab, uint8_t alm) const; // lab.cc bool is_lab_ctrlset_legal(uint32_t lab) const; // lab.cc bool check_lab_input_count(uint32_t lab) const; // lab.cc + bool check_mlab_groups(uint32_t lab) const; // lab.cc void assign_comb_info(CellInfo *cell) const; // lab.cc void assign_ff_info(CellInfo *cell) const; // lab.cc @@ -480,6 +482,10 @@ struct Arch : BaseArch<ArchRanges> uint64_t compute_lut_mask(uint32_t lab, uint8_t alm); // lab.cc + // Keeping track of unique MLAB write ports to assign them indices + dict<IdString, IdString> get_mlab_key(const CellInfo *cell, bool include_raddr = false) const; // lab.cc + mutable idict<dict<IdString, IdString>> mlab_groups; + // ------------------------------------------------- bool is_io_cell(IdString cell_type) const; // io.cc |