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authorgatecat <gatecat@ds0.me>2021-05-09 16:27:57 +0100
committergatecat <gatecat@ds0.me>2021-05-15 14:54:33 +0100
commitc5d983066df541ad93a13904e96e0298489e2fcd (patch)
treef0acc0724f6152fd14610bcbe5e812397177bb0d /mistral/arch.h
parent2612853238af4c84fa38c1c5e349fa19c5c51ebe (diff)
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mistral: Some preps for generating bitstreams
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral/arch.h')
-rw-r--r--mistral/arch.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/mistral/arch.h b/mistral/arch.h
index 868d8650..860b3327 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -40,6 +40,10 @@ struct ArchArgs
// These structures are used for fast ALM validity checking
struct ALMInfo
{
+ // Wires, so bitstream gen can determine connectivity
+ std::array<WireId, 2> comb_out;
+ std::array<WireId, 2> sel_clk, sel_ena, sel_aclr, sel_ef;
+ std::array<WireId, 4> ff_in, ff_out;
// Pointers to bels
std::array<BelId, 2> lut_bels;
std::array<BelId, 4> ff_bels;
@@ -326,6 +330,8 @@ struct Arch : BaseArch<ArchRanges>
const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return wires.at(wire).bel_pins; }
AllWireRange getWires() const override { return AllWireRange(wires); }
+ bool wires_connected(WireId src, WireId dst) const;
+
// -------------------------------------------------
PipId getPipByName(IdStringList name) const override;
@@ -461,9 +467,15 @@ struct Arch : BaseArch<ArchRanges>
static const std::unordered_map<IdString, CellPinsData> cell_pins_db; // pins.cc
CellPinStyle get_cell_pin_style(const CellInfo *cell, IdString port) const; // pins.cc
+ // -------------------------------------------------
+
// List of IO constraints, used by QSF parser
std::unordered_map<IdString, std::unordered_map<IdString, Property>> io_attr;
void read_qsf(std::istream &in); // qsf.cc
+
+ // -------------------------------------------------
+
+ void init_base_bitstream(); // base_bitstream.cc
};
NEXTPNR_NAMESPACE_END