refactor: Use constids instead of id("..")

Signed-off-by: gatecat <gatecat@ds0.me>

7 files changed, 81 insertions, 64 deletions

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 6c0e48ce..5fcdeaf7 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -171,17 +171,17 @@ std::string Arch::get_full_chip_name() const
 IdString Arch::archArgsToId(ArchArgs args) const
 {
     if (args.type == ArchArgs::LCMXO2_256HC) {
-        return id("lcmxo2_256hc");
+        return id_lcmxo2_256hc;
     } else if (args.type == ArchArgs::LCMXO2_640HC) {
-        return id("lcmxo2_640hc");
+        return id_lcmxo2_640hc;
     } else if (args.type == ArchArgs::LCMXO2_1200HC) {
-        return id("lcmxo2_1200hc");
+        return id_lcmxo2_1200hc;
     } else if (args.type == ArchArgs::LCMXO2_2000HC) {
-        return id("lcmxo2_2000hc");
+        return id_lcmxo2_2000hc;
     } else if (args.type == ArchArgs::LCMXO2_4000HC) {
-        return id("lcmxo2_4000hc");
+        return id_lcmxo2_4000hc;
     } else if (args.type == ArchArgs::LCMXO2_7000HC) {
-        return id("lcmxo2_7000hc");
+        return id_lcmxo2_7000hc;
     }
 
     return IdString();
@@ -414,17 +414,17 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 bool Arch::place()
 {
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
     if (placer == "sa") {
         bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
-        getCtx()->settings[getCtx()->id("place")] = 1;
+        getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
         return retVal;
     } else if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
         cfg.ioBufTypes.insert(id_FACADE_IO);
         bool retVal = placer_heap(getCtx(), cfg);
-        getCtx()->settings[getCtx()->id("place")] = 1;
+        getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
         return retVal;
     } else {
@@ -434,7 +434,7 @@ bool Arch::place()
 
 bool Arch::route()
 {
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -444,7 +444,7 @@ bool Arch::route()
     } else {
         log_error("MachXO2 architecture does not support router '%s'\n", router.c_str());
     }
-    getCtx()->settings[getCtx()->id("route")] = 1;
+    getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
     return result;
 }
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 29d8c3ff..347f4ede 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -435,7 +435,7 @@ struct Arch : BaseArch<ArchRanges>
     // Extra helper
     std::string get_full_chip_name() const;
 
-    IdString archId() const override { return id("machxo2"); }
+    IdString archId() const override { return id_machxo2; }
     ArchArgs archArgs() const override { return args; }
     IdString archArgsToId(ArchArgs args) const override;
 
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index f624d91b..9a711cbe 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -235,36 +235,34 @@ void write_bitstream(Context *ctx, std::string text_config_file)
             int int_index = slice[5] - 'A';
             NPNR_ASSERT(int_index >= 0 && int_index < 4);
 
-            int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
-            int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
+            int lut0_init = int_or_default(ci->params, id_LUT0_INITVAL);
+            int lut1_init = int_or_default(ci->params, id_LUT1_INITVAL);
             cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
             cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
-            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
-            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
+            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
+            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
             cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".SRMODE",
-                                     str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
-            cc.tiles[tname].add_enum(slice + ".CEMUX", intstr_or_default(ci->params, ctx->id("CEMUX"), "1"));
+                                     str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+            cc.tiles[tname].add_enum(slice + ".CEMUX", intstr_or_default(ci->params, id_CEMUX, "1"));
             cc.tiles[tname].add_enum("CLK" + std::to_string(int_index) + ".CLKMUX",
-                                     intstr_or_default(ci->params, ctx->id("CLKMUX"), "0"));
+                                     intstr_or_default(ci->params, id_CLKMUX, "0"));
             cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".LSRMUX",
-                                     str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+                                     str_or_default(ci->params, id_LSRMUX, "LSR"));
             cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".LSRONMUX",
-                                     intstr_or_default(ci->params, ctx->id("LSRONMUX"), "LSRMUX"));
-            cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, ctx->id("REGMODE"), "FF"));
-            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, ctx->id("REG0_SD"), "0"));
-            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, ctx->id("REG1_SD"), "0"));
-            cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
-                                     str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
-                                     str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
-        } else if (ci->type == ctx->id("FACADE_IO")) {
+                                     intstr_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+            cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
+            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, id_REG0_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
+            cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
+        } else if (ci->type == id_FACADE_IO) {
             std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
-            std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
-            std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
+            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
             std::string pic_tile = get_pic_tile(ctx, bel);
             cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
-        } else if (ci->type == ctx->id("OSCH")) {
-            std::string freq = str_or_default(ci->params, ctx->id("NOM_FREQ"), "2.08");
+        } else if (ci->type == id_OSCH) {
+            std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
             cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
             cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
         }
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index bbe3f2d6..1c4f753b 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -103,12 +103,12 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_WADO3);
     } else if (type == id_FACADE_IO) {
         new_cell->params[id_DIR] = std::string("INPUT");
-        new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
+        new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
 
-        new_cell->addInout(ctx->id("PAD"));
-        new_cell->addInput(ctx->id("I"));
-        new_cell->addInput(ctx->id("EN"));
-        new_cell->addOutput(ctx->id("O"));
+        new_cell->addInout(id_PAD);
+        new_cell->addInput(id_I);
+        new_cell->addInput(id_EN);
+        new_cell->addOutput(id_O);
     } else if (type == id_LUT4) {
         new_cell->params[id_INIT] = Property(0, 16);
 
@@ -126,7 +126,7 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
 
 void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
 {
-    lc->params[ctx->id("LUT0_INITVAL")] = lut->params[ctx->id("INIT")];
+    lc->params[id_LUT0_INITVAL] = lut->params[id_INIT];
 
     for (std::string i : {"A", "B", "C", "D"}) {
         IdString lut_port = ctx->id(i);
@@ -134,34 +134,34 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
         replace_port(lut, lut_port, lc, lc_port);
     }
 
-    replace_port(lut, ctx->id("Z"), lc, ctx->id("F0"));
+    replace_port(lut, id_Z, lc, id_F0);
 }
 
 void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
 {
     // FIXME: This will have to change once we support FFs with reset value of 1.
-    lc->params[ctx->id("REG0_REGSET")] = std::string("RESET");
+    lc->params[id_REG0_REGSET] = std::string("RESET");
 
-    replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
-    replace_port(dff, ctx->id("LSR"), lc, ctx->id("LSR"));
-    replace_port(dff, ctx->id("Q"), lc, ctx->id("Q0"));
+    replace_port(dff, id_CLK, lc, id_CLK);
+    replace_port(dff, id_LSR, lc, id_LSR);
+    replace_port(dff, id_Q, lc, id_Q0);
 
     if (lut_type == LutType::PassThru) {
         // If a register's DI port is fed by a constant, options for placing are
         // limited. Use the LUT to get around this.
         // LUT output will go to F0, which will feed back to DI0 input.
-        lc->params[ctx->id("LUT0_INITVAL")] = Property(0xAAAA, 16);
-        replace_port(dff, ctx->id("DI"), lc, ctx->id("A0"));
-        connect_ports(ctx, lc, ctx->id("F0"), lc, ctx->id("DI0"));
+        lc->params[id_LUT0_INITVAL] = Property(0xAAAA, 16);
+        replace_port(dff, id_DI, lc, id_A0);
+        connect_ports(ctx, lc, id_F0, lc, id_DI0);
     } else if (lut_type == LutType::None) {
         // If there is no LUT, use the M0 input because DI0 requires
         // going through the LUTs.
-        lc->params[ctx->id("REG0_SD")] = std::string("0");
-        replace_port(dff, ctx->id("DI"), lc, ctx->id("M0"));
+        lc->params[id_REG0_SD] = std::string("0");
+        replace_port(dff, id_DI, lc, id_M0);
     } else {
         // Otherwise, there's a LUT being used in the slice and mapping DI to
         // DI0 input is fine.
-        replace_port(dff, ctx->id("DI"), lc, ctx->id("DI0"));
+        replace_port(dff, id_DI, lc, id_DI0);
     }
 }
 
diff --git a/machxo2/cells.h b/machxo2/cells.h
index 409b68b1..7a9bab92 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -40,12 +40,12 @@ enum class LutType
 std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
-inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT4"); }
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
 
 // Return true if a cell is a flipflop
-inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("FACADE_FF"); }
+inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_FF; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("FACADE_SLICE"); }
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_SLICE; }
 
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index b2ff51ae..b216f8b4 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -116,3 +116,22 @@ X(CLK0)
 X(CLK1)
 X(SEL)
 X(DCMOUT)
+
+X(BEL)
+X(GND)
+X(IO_TYPE)
+X(LOC)
+X(NOM_FREQ)
+X(VCC)
+X(lcmxo2_1200hc)
+X(lcmxo2_2000hc)
+X(lcmxo2_256hc)
+X(lcmxo2_4000hc)
+X(lcmxo2_640hc)
+X(lcmxo2_7000hc)
+X(machxo2)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 0c2c9459..de607865 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -51,20 +51,20 @@ static void pack_lut_lutffs(Context *ctx)
             // LUT4 drives more than one FF.
             NetInfo *o = ci->ports.at(id_Z).net;
             CellInfo *dff = net_only_drives(ctx, o, is_ff, id_DI, false);
-            auto lut_bel = ci->attrs.find(ctx->id("BEL"));
+            auto lut_bel = ci->attrs.find(id_BEL);
             bool packed_dff = false;
 
             if (dff) {
                 if (ctx->verbose)
                     log_info("found attached dff %s\n", dff->name.c_str(ctx));
-                auto dff_bel = dff->attrs.find(ctx->id("BEL"));
+                auto dff_bel = dff->attrs.find(id_BEL);
                 if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
                     // Locations don't match, can't pack
                 } else {
                     lut_to_lc(ctx, ci, packed.get(), false);
                     dff_to_lc(ctx, dff, packed.get(), LutType::Normal);
                     if (dff_bel != dff->attrs.end())
-                        packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                        packed->attrs[id_BEL] = dff_bel->second;
                     packed_cells.insert(dff->name);
                     if (ctx->verbose)
                         log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
@@ -104,12 +104,12 @@ static void pack_remaining_ffs(Context *ctx)
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
 
-            auto dff_bel = ci->attrs.find(ctx->id("BEL"));
+            auto dff_bel = ci->attrs.find(id_BEL);
 
             dff_to_lc(ctx, ci, packed.get(), LutType::None);
 
             if (dff_bel != ci->attrs.end())
-                packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                packed->attrs[id_BEL] = dff_bel->second;
             packed_cells.insert(ci->name);
             if (ctx->verbose)
                 log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
@@ -198,12 +198,12 @@ static void pack_constants(Context *ctx)
 
     for (auto &net : ctx->nets) {
         NetInfo *ni = net.second.get();
-        if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, gnd_net, false);
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
-        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, vcc_net, true);
             dead_nets.push_back(net.first);
@@ -294,8 +294,8 @@ static void pack_io(Context *ctx)
             // attribute already on a FACADE_IO is an error. Attributes on
             // the pin attached to the PAD of FACADE_IO are ignored by this
             // packing phase.
-            auto loc_attr_cell = ci->attrs.find(ctx->id("LOC"));
-            auto bel_attr_cell = ci->attrs.find(ctx->id("BEL"));
+            auto loc_attr_cell = ci->attrs.find(id_LOC);
+            auto bel_attr_cell = ci->attrs.find(id_BEL);
 
             if (loc_attr_cell != ci->attrs.end()) {
                 if (bel_attr_cell != ci->attrs.end()) {
@@ -312,7 +312,7 @@ static void pack_io(Context *ctx)
                 } else {
                     log_info("pin '%s' constrained to Bel '%s'.\n", ci->name.c_str(ctx), ctx->nameOfBel(pinBel));
                 }
-                ci->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
+                ci->attrs[id_BEL] = ctx->getBelName(pinBel).str(ctx);
             }
         }
     }
@@ -332,7 +332,7 @@ bool Arch::pack()
         pack_io(ctx);
         pack_lut_lutffs(ctx);
         pack_remaining_ffs(ctx);
-        ctx->settings[ctx->id("pack")] = 1;
+        ctx->settings[id_pack] = 1;
         ctx->assignArchInfo();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         return true;