machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top".

1 files changed, 9 insertions, 9 deletions

diff --git a/machxo2/examples/rgbcount.v b/machxo2/examples/rgbcount.v
index 230fc73c..bf5c7518 100644
--- a/machxo2/examples/rgbcount.v
+++ b/machxo2/examples/rgbcount.v
@@ -2,7 +2,7 @@
 // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
 // https://tinyfpga.com/a-series-guide.html used as a basis.
 
-module TinyFPGA_A2 (
+module top (
   (* LOC="21" *)
   inout pin6,
   (* LOC="26" *)
@@ -11,23 +11,23 @@ module TinyFPGA_A2 (
   inout pin10_sda,
 );
   wire clk;
-  
+
   OSCH #(
     .NOM_FREQ("2.08")
   ) internal_oscillator_inst (
-    .STDBY(1'b0), 
+    .STDBY(1'b0),
     .OSC(clk)
-  ); 
-  
+  );
+
   reg [23:0] led_timer;
-  
+
   always @(posedge clk) begin
-    led_timer <= led_timer + 1; 
+    led_timer <= led_timer + 1;
   end
-  
+
   // left side of board
   assign pin9_jtgnb = led_timer[23];
   assign pin10_sda = led_timer[22];
   assign pin6 = led_timer[21];
 
-endmodule
\ No newline at end of file
+endmodule