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author | gatecat <gatecat@ds0.me> | 2021-02-11 11:34:08 +0000 |
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committer | gatecat <gatecat@ds0.me> | 2021-02-12 10:36:59 +0000 |
commit | 3f7618283d1eed2a35bbce161f905a4088020d8e (patch) | |
tree | 85b57c898358842f7b217090eab8e2638bcf1336 /machxo2/bitstream.cc | |
parent | 32433db7aeda19e7f37f4e21f084f6017e85030b (diff) | |
download | nextpnr-3f7618283d1eed2a35bbce161f905a4088020d8e.tar.gz nextpnr-3f7618283d1eed2a35bbce161f905a4088020d8e.tar.bz2 nextpnr-3f7618283d1eed2a35bbce161f905a4088020d8e.zip |
machxo2: Update with Arch API changes
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'machxo2/bitstream.cc')
-rw-r--r-- | machxo2/bitstream.cc | 36 |
1 files changed, 14 insertions, 22 deletions
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index a095333a..1711326f 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -60,24 +60,15 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose // relative coords push them outside the bounds of the chip. auto is_pio_wire = [](std::string name) { - return ( - name.find("DI") != std::string::npos || - name.find("JDI") != std::string::npos || - name.find("PADD") != std::string::npos || - name.find("INDD") != std::string::npos || - name.find("IOLDO") != std::string::npos || - name.find("IOLTO") != std::string::npos || - name.find("JCE") != std::string::npos || - name.find("JCLK") != std::string::npos || - name.find("JLSR") != std::string::npos || - name.find("JONEG") != std::string::npos || - name.find("JOPOS") != std::string::npos || - name.find("JTS") != std::string::npos || - name.find("JIN") != std::string::npos || - name.find("JIP") != std::string::npos || - // Connections to global mux - name.find("JINCK") != std::string::npos - ); + return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos || + name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos || + name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos || + name.find("JCE") != std::string::npos || name.find("JCLK") != std::string::npos || + name.find("JLSR") != std::string::npos || name.find("JONEG") != std::string::npos || + name.find("JOPOS") != std::string::npos || name.find("JTS") != std::string::npos || + name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos || + // Connections to global mux + name.find("JINCK") != std::string::npos); }; if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix2 == "U_" || prefix2 == "D_" || @@ -85,10 +76,10 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) return basename; if (loc == wire.location) { // TODO: JINCK is not currently handled by this. - if(is_pio_wire(basename)) { - if(wire.location.x == 0) + if (is_pio_wire(basename)) { + if (wire.location.x == 0) return "W1_" + basename; - else if(wire.location.x == max_col) + else if (wire.location.x == max_col) return "E1_" + basename; } return basename; @@ -200,7 +191,8 @@ void write_bitstream(Context *ctx, std::string text_config_file) for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); if (ci->bel == BelId()) { - log_warning("found unplaced cell '%s' during bitstream gen. Not writing to bitstream.\n", ci->name.c_str(ctx)); + log_warning("found unplaced cell '%s' during bitstream gen. Not writing to bitstream.\n", + ci->name.c_str(ctx)); continue; } BelId bel = ci->bel; |