diff options
author | Miodrag Milanovic <mmicko@gmail.com> | 2018-06-25 21:33:48 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2018-06-25 21:33:48 +0200 |
commit | db890d3a81bfe6760e9f4ea981798269abb60a20 (patch) | |
tree | ddae875c970642d6b79bb09ae201abe5f280c050 /ice40 | |
parent | 64208da1f986f104682c9c050c43f2273900810a (diff) | |
download | nextpnr-db890d3a81bfe6760e9f4ea981798269abb60a20.tar.gz nextpnr-db890d3a81bfe6760e9f4ea981798269abb60a20.tar.bz2 nextpnr-db890d3a81bfe6760e9f4ea981798269abb60a20.zip |
nets and cells are unique_ptr's
Diffstat (limited to 'ice40')
-rw-r--r-- | ice40/arch_place.cc | 6 | ||||
-rw-r--r-- | ice40/bitstream.cc | 34 | ||||
-rw-r--r-- | ice40/cells.cc | 92 | ||||
-rw-r--r-- | ice40/cells.h | 2 | ||||
-rw-r--r-- | ice40/pack.cc | 132 |
5 files changed, 132 insertions, 134 deletions
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 129ebe18..4160a644 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -91,7 +91,7 @@ bool Arch::isBelLocationValid(BelId bel) const for (auto bel_other : getBelsAtSameTile(bel)) { IdString cell_other = getBoundBelCell(bel_other); if (cell_other != IdString()) { - const CellInfo *ci_other = cells.at(cell_other); + const CellInfo *ci_other = cells.at(cell_other).get(); bel_cells.push_back(ci_other); } } @@ -101,7 +101,7 @@ bool Arch::isBelLocationValid(BelId bel) const if (cellId == IdString()) return true; else - return isValidBelForCell(cells.at(cellId), bel); + return isValidBelForCell(cells.at(cellId).get(), bel); } } @@ -115,7 +115,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const for (auto bel_other : getBelsAtSameTile(bel)) { IdString cell_other = getBoundBelCell(bel_other); if (cell_other != IdString() && bel_other != bel) { - const CellInfo *ci_other = cells.at(cell_other); + const CellInfo *ci_other = cells.at(cell_other).get(); bel_cells.push_back(ci_other); } } diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 0e387c72..609741fe 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -140,8 +140,8 @@ void write_asc(const Context *ctx, std::ostream &out) } } // Set logic cell config - for (auto cell : ctx->cells) { - BelId bel = cell.second->bel; + for (auto& cell : ctx->cells) { + BelId bel = cell.second.get()->bel; if (bel == BelId()) { std::cout << "Found unplaced cell " << cell.first.str(ctx) << " while generating bitstream!" << std::endl; continue; @@ -150,12 +150,12 @@ void write_asc(const Context *ctx, std::ostream &out) int x = beli.x, y = beli.y, z = beli.z; if (cell.second->type == ctx->id("ICESTORM_LC")) { const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; - unsigned lut_init = get_param_or_def(cell.second, ctx->id("LUT_INIT")); - bool neg_clk = get_param_or_def(cell.second, ctx->id("NEG_CLK")); - bool dff_enable = get_param_or_def(cell.second, ctx->id("DFF_ENABLE")); - bool async_sr = get_param_or_def(cell.second, ctx->id("ASYNC_SR")); - bool set_noreset = get_param_or_def(cell.second, ctx->id("SET_NORESET")); - bool carry_enable = get_param_or_def(cell.second, ctx->id("CARRY_ENABLE")); + unsigned lut_init = get_param_or_def(cell.second.get(), ctx->id("LUT_INIT")); + bool neg_clk = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK")); + bool dff_enable = get_param_or_def(cell.second.get(), ctx->id("DFF_ENABLE")); + bool async_sr = get_param_or_def(cell.second.get(), ctx->id("ASYNC_SR")); + bool set_noreset = get_param_or_def(cell.second.get(), ctx->id("SET_NORESET")); + bool carry_enable = get_param_or_def(cell.second.get(), ctx->id("CARRY_ENABLE")); std::vector<bool> lc(20, false); // From arachne-pnr static std::vector<int> lut_perm = { @@ -176,9 +176,9 @@ void write_asc(const Context *ctx, std::ostream &out) set_config(ti, config.at(y).at(x), "NegClk", neg_clk); } else if (cell.second->type == ctx->id("SB_IO")) { const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; - unsigned pin_type = get_param_or_def(cell.second, ctx->id("PIN_TYPE")); - bool neg_trigger = get_param_or_def(cell.second, ctx->id("NEG_TRIGGER")); - bool pullup = get_param_or_def(cell.second, ctx->id("PULLUP")); + unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE")); + bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER")); + bool pullup = get_param_or_def(cell.second.get(), ctx->id("PULLUP")); for (int i = 0; i < 6; i++) { bool val = (pin_type >> i) & 0x01; set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val); @@ -220,10 +220,10 @@ void write_asc(const Context *ctx, std::ostream &out) if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) { set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true); } - bool negclk_r = get_param_or_def(cell.second, ctx->id("NEG_CLK_R")); - bool negclk_w = get_param_or_def(cell.second, ctx->id("NEG_CLK_W")); - int write_mode = get_param_or_def(cell.second, ctx->id("WRITE_MODE")); - int read_mode = get_param_or_def(cell.second, ctx->id("READ_MODE")); + bool negclk_r = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_R")); + bool negclk_w = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_W")); + int write_mode = get_param_or_def(cell.second.get(), ctx->id("WRITE_MODE")); + int read_mode = get_param_or_def(cell.second.get(), ctx->id("READ_MODE")); set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); @@ -371,7 +371,7 @@ void write_asc(const Context *ctx, std::ostream &out) } // Write RAM init data - for (auto cell : ctx->cells) { + for (auto& cell : ctx->cells) { if (cell.second->bel != BelId()) { if (cell.second->type == ctx->id("ICESTORM_RAM")) { const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index]; @@ -380,7 +380,7 @@ void write_asc(const Context *ctx, std::ostream &out) for (int w = 0; w < 16; w++) { std::vector<bool> bits(256); std::string init = - get_param_str_or_def(cell.second, ctx->id(std::string("INIT_") + get_hexdigit(w))); + get_param_str_or_def(cell.second.get(), ctx->id(std::string("INIT_") + get_hexdigit(w))); assert(init != ""); for (size_t i = 0; i < init.size(); i++) { bool val = (init.at((init.size() - 1) - i) == '1'); diff --git a/ice40/cells.cc b/ice40/cells.cc index e9c75649..4ca579f6 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -30,10 +30,10 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir cell->ports[id] = PortInfo{id, nullptr, dir}; } -CellInfo *create_ice_cell(Context *ctx, IdString type, std::string name) +std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name) { static int auto_idx = 0; - CellInfo *new_cell = new CellInfo(); + std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo()); if (name.empty()) { new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)); } else { @@ -50,84 +50,84 @@ CellInfo *create_ice_cell(Context *ctx, IdString type, std::string name) new_cell->params[ctx->id("CIN_CONST")] = "0"; new_cell->params[ctx->id("CIN_SET")] = "0"; - add_port(ctx, new_cell, "I0", PORT_IN); - add_port(ctx, new_cell, "I1", PORT_IN); - add_port(ctx, new_cell, "I2", PORT_IN); - add_port(ctx, new_cell, "I3", PORT_IN); - add_port(ctx, new_cell, "CIN", PORT_IN); + add_port(ctx, new_cell.get(), "I0", PORT_IN); + add_port(ctx, new_cell.get(), "I1", PORT_IN); + add_port(ctx, new_cell.get(), "I2", PORT_IN); + add_port(ctx, new_cell.get(), "I3", PORT_IN); + add_port(ctx, new_cell.get(), "CIN", PORT_IN); - add_port(ctx, new_cell, "CLK", PORT_IN); - add_port(ctx, new_cell, "CEN", PORT_IN); - add_port(ctx, new_cell, "SR", PORT_IN); + add_port(ctx, new_cell.get(), "CLK", PORT_IN); + add_port(ctx, new_cell.get(), "CEN", PORT_IN); + add_port(ctx, new_cell.get(), "SR", PORT_IN); - add_port(ctx, new_cell, "LO", PORT_OUT); - add_port(ctx, new_cell, "O", PORT_OUT); - add_port(ctx, new_cell, "OUT", PORT_OUT); + add_port(ctx, new_cell.get(), "LO", PORT_OUT); + add_port(ctx, new_cell.get(), "O", PORT_OUT); + add_port(ctx, new_cell.get(), "OUT", PORT_OUT); } else if (type == ctx->id("SB_IO")) { new_cell->params[ctx->id("PIN_TYPE")] = "0"; new_cell->params[ctx->id("PULLUP")] = "0"; new_cell->params[ctx->id("NEG_TRIGGER")] = "0"; new_cell->params[ctx->id("IOSTANDARD")] = "SB_LVCMOS"; - add_port(ctx, new_cell, "PACKAGE_PIN", PORT_INOUT); + add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT); - add_port(ctx, new_cell, "LATCH_INPUT_VALUE", PORT_IN); - add_port(ctx, new_cell, "CLOCK_ENABLE", PORT_IN); - add_port(ctx, new_cell, "INPUT_CLK", PORT_IN); - add_port(ctx, new_cell, "OUTPUT_CLK", PORT_IN); + add_port(ctx, new_cell.get(), "LATCH_INPUT_VALUE", PORT_IN); + add_port(ctx, new_cell.get(), "CLOCK_ENABLE", PORT_IN); + add_port(ctx, new_cell.get(), "INPUT_CLK", PORT_IN); + add_port(ctx, new_cell.get(), "OUTPUT_CLK", PORT_IN); - add_port(ctx, new_cell, "OUTPUT_ENABLE", PORT_IN); - add_port(ctx, new_cell, "D_OUT_0", PORT_IN); - add_port(ctx, new_cell, "D_OUT_1", PORT_IN); + add_port(ctx, new_cell.get(), "OUTPUT_ENABLE", PORT_IN); + add_port(ctx, new_cell.get(), "D_OUT_0", PORT_IN); + add_port(ctx, new_cell.get(), "D_OUT_1", PORT_IN); - add_port(ctx, new_cell, "D_IN_0", PORT_OUT); - add_port(ctx, new_cell, "D_IN_1", PORT_OUT); + add_port(ctx, new_cell.get(), "D_IN_0", PORT_OUT); + add_port(ctx, new_cell.get(), "D_IN_1", PORT_OUT); } else if (type == ctx->id("ICESTORM_RAM")) { new_cell->params[ctx->id("NEG_CLK_W")] = "0"; new_cell->params[ctx->id("NEG_CLK_R")] = "0"; new_cell->params[ctx->id("WRITE_MODE")] = "0"; new_cell->params[ctx->id("READ_MODE")] = "0"; - add_port(ctx, new_cell, "RCLK", PORT_IN); - add_port(ctx, new_cell, "RCLKE", PORT_IN); - add_port(ctx, new_cell, "RE", PORT_IN); + add_port(ctx, new_cell.get(), "RCLK", PORT_IN); + add_port(ctx, new_cell.get(), "RCLKE", PORT_IN); + add_port(ctx, new_cell.get(), "RE", PORT_IN); - add_port(ctx, new_cell, "WCLK", PORT_IN); - add_port(ctx, new_cell, "WCLKE", PORT_IN); - add_port(ctx, new_cell, "WE", PORT_IN); + add_port(ctx, new_cell.get(), "WCLK", PORT_IN); + add_port(ctx, new_cell.get(), "WCLKE", PORT_IN); + add_port(ctx, new_cell.get(), "WE", PORT_IN); for (int i = 0; i < 16; i++) { - add_port(ctx, new_cell, "WDATA_" + std::to_string(i), PORT_IN); - add_port(ctx, new_cell, "MASK_" + std::to_string(i), PORT_IN); - add_port(ctx, new_cell, "RDATA_" + std::to_string(i), PORT_OUT); + add_port(ctx, new_cell.get(), "WDATA_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "MASK_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "RDATA_" + std::to_string(i), PORT_OUT); } for (int i = 0; i < 11; i++) { - add_port(ctx, new_cell, "RADDR_" + std::to_string(i), PORT_IN); - add_port(ctx, new_cell, "WADDR_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "RADDR_" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "WADDR_" + std::to_string(i), PORT_IN); } } else if (type == ctx->id("ICESTORM_LFOSC")) { - add_port(ctx, new_cell, "CLKLFEN", PORT_IN); - add_port(ctx, new_cell, "CLKLFPU", PORT_IN); - add_port(ctx, new_cell, "CLKLF", PORT_OUT); - add_port(ctx, new_cell, "CLKLF_FABRIC", PORT_OUT); + add_port(ctx, new_cell.get(), "CLKLFEN", PORT_IN); + add_port(ctx, new_cell.get(), "CLKLFPU", PORT_IN); + add_port(ctx, new_cell.get(), "CLKLF", PORT_OUT); + add_port(ctx, new_cell.get(), "CLKLF_FABRIC", PORT_OUT); } else if (type == ctx->id("ICESTORM_HFOSC")) { new_cell->params[ctx->id("CLKHF_DIV")] = "0"; new_cell->params[ctx->id("TRIM_EN")] = "0"; - add_port(ctx, new_cell, "CLKHFEN", PORT_IN); - add_port(ctx, new_cell, "CLKHFPU", PORT_IN); - add_port(ctx, new_cell, "CLKHF", PORT_OUT); - add_port(ctx, new_cell, "CLKHF_FABRIC", PORT_OUT); + add_port(ctx, new_cell.get(), "CLKHFEN", PORT_IN); + add_port(ctx, new_cell.get(), "CLKHFPU", PORT_IN); + add_port(ctx, new_cell.get(), "CLKHF", PORT_OUT); + add_port(ctx, new_cell.get(), "CLKHF_FABRIC", PORT_OUT); for (int i = 0; i < 10; i++) - add_port(ctx, new_cell, "TRIM" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "TRIM" + std::to_string(i), PORT_IN); } else if (type == ctx->id("SB_GB")) { - add_port(ctx, new_cell, "USER_SIGNAL_TO_GLOBAL_BUFFER", PORT_IN); - add_port(ctx, new_cell, "GLOBAL_BUFFER_OUTPUT", PORT_OUT); + add_port(ctx, new_cell.get(), "USER_SIGNAL_TO_GLOBAL_BUFFER", PORT_IN); + add_port(ctx, new_cell.get(), "GLOBAL_BUFFER_OUTPUT", PORT_OUT); } else { log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); } - return new_cell; + return std::move(new_cell); } void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff) diff --git a/ice40/cells.h b/ice40/cells.h index a8891598..eb0007aa 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -27,7 +27,7 @@ NEXTPNR_NAMESPACE_BEGIN // Create a standard iCE40 cell and return it // Name will be automatically assigned if not specified -CellInfo *create_ice_cell(Context *ctx, IdString type, std::string name = ""); +std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name = ""); // Return true if a cell is a LUT inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LUT4"); } diff --git a/ice40/pack.cc b/ice40/pack.cc index d0419098..43960d9f 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -34,16 +34,15 @@ static void pack_lut_lutffs(Context *ctx) log_info("Packing LUT-FFs..\n"); std::unordered_set<IdString> packed_cells; - std::vector<CellInfo *> new_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (ctx->verbose) log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx)); if (is_lut(ctx, ci)) { - CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_LC"); + std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_LC"); std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); packed_cells.insert(ci->name); - new_cells.push_back(packed); if (ctx->verbose) log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx)); // See if we can pack into a DFF @@ -59,8 +58,8 @@ static void pack_lut_lutffs(Context *ctx) if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) { // Locations don't match, can't pack } else { - lut_to_lc(ctx, ci, packed, false); - dff_to_lc(ctx, dff, packed, false); + lut_to_lc(ctx, ci, packed.get(), false); + dff_to_lc(ctx, dff, packed.get(), false); ctx->nets.erase(o->name); if (dff_bel != dff->attrs.end()) packed->attrs[ctx->id("BEL")] = dff_bel->second; @@ -71,15 +70,16 @@ static void pack_lut_lutffs(Context *ctx) } } if (!packed_dff) { - lut_to_lc(ctx, ci, packed, true); + lut_to_lc(ctx, ci, packed.get(), true); } + new_cells.push_back(std::move(packed)); } } for (auto pcell : packed_cells) { ctx->cells.erase(pcell); } - for (auto ncell : new_cells) { - ctx->cells[ncell->name] = ncell; + for (auto& ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); } } @@ -89,25 +89,25 @@ static void pack_nonlut_ffs(Context *ctx) log_info("Packing non-LUT FFs..\n"); std::unordered_set<IdString> packed_cells; - std::vector<CellInfo *> new_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_ff(ctx, ci)) { - CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_DFFLC"); + std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_DFFLC"); std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); if (ctx->verbose) log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx)); packed_cells.insert(ci->name); - new_cells.push_back(packed); - dff_to_lc(ctx, ci, packed, true); + dff_to_lc(ctx, ci, packed.get(), true); + new_cells.push_back(std::move(packed)); } } for (auto pcell : packed_cells) { ctx->cells.erase(pcell); } - for (auto ncell : new_cells) { - ctx->cells[ncell->name] = ncell; + for (auto& ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); } } @@ -122,7 +122,7 @@ static void pack_carries(Context *ctx) CellInfo *ci = cell.second; if (is_carry(ctx, ci)) { packed_cells.insert(cell.first); - CellInfo *carry_ci_lc = net_only_drives(ctx, ci->ports.at(ctx->id("CI")).net, is_lc, ctx->id("I3"), false); + CellInfo * carry_ci_lc = net_only_drives(ctx, ci->ports.at(ctx->id("CI")).net, is_lc, ctx->id("I3"), false); if (!ci->ports.at(ctx->id("I0")).net) log_error("SB_CARRY '%s' has disconnected port I0\n", cell.first.c_str(ctx)); if (!ci->ports.at(ctx->id("I1")).net) @@ -156,7 +156,7 @@ static void pack_carries(Context *ctx) log_error("SB_CARRY '%s' cannot be packed into any logic " "cell (no logic cell connects to both I0 and I1)\n", cell.first.c_str(ctx)); - carry_lc = ctx->cells.at(*carry_lcs.begin()); + carry_lc = ctx->cells.at(*carry_lcs.begin()).get(); } carry_lc->attrs[ctx->id("CARRY_ENABLE")] = "1"; replace_port(ci, ctx->id("CI"), carry_lc, ctx->id("CIN")); @@ -182,14 +182,13 @@ static void pack_ram(Context *ctx) log_info("Packing RAMs..\n"); std::unordered_set<IdString> packed_cells; - std::vector<CellInfo *> new_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_ram(ctx, ci)) { - CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_RAM"), ci->name.str(ctx) + "_RAM"); + std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_RAM"), ci->name.str(ctx) + "_RAM"); packed_cells.insert(ci->name); - new_cells.push_back(packed); for (auto param : ci->params) packed->params[param.first] = param.second; packed->params[ctx->id("NEG_CLK_W")] = @@ -204,16 +203,17 @@ static void pack_ram(Context *ctx) if (bpos != std::string::npos) { newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2); } - replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed, ctx->id(newname)); + replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname)); } + new_cells.push_back(std::move(packed)); } } for (auto pcell : packed_cells) { ctx->cells.erase(pcell); } - for (auto ncell : new_cells) { - ctx->cells[ncell->name] = ncell; + for (auto& ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); } } @@ -242,18 +242,18 @@ static void pack_constants(Context *ctx) { log_info("Packing constants..\n"); - CellInfo *gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND"); + std::unique_ptr<CellInfo> gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND"); gnd_cell->params[ctx->id("LUT_INIT")] = "0"; - NetInfo *gnd_net = new NetInfo; + std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo); gnd_net->name = ctx->id("$PACKER_GND_NET"); - gnd_net->driver.cell = gnd_cell; + gnd_net->driver.cell = gnd_cell.get(); gnd_net->driver.port = ctx->id("O"); - CellInfo *vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC"); + std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC"); vcc_cell->params[ctx->id("LUT_INIT")] = "1"; - NetInfo *vcc_net = new NetInfo; + std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo); vcc_net->name = ctx->id("$PACKER_VCC_NET"); - vcc_net->driver.cell = vcc_cell; + vcc_net->driver.cell = vcc_cell.get(); vcc_net->driver.port = ctx->id("O"); std::vector<IdString> dead_nets; @@ -264,29 +264,26 @@ static void pack_constants(Context *ctx) NetInfo *ni = net.second; if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) { IdString drv_cell = ni->driver.cell->name; - set_net_constant(ctx, ni, gnd_net, false); + set_net_constant(ctx, ni, gnd_net.get(), false); gnd_used = true; dead_nets.push_back(net.first); ctx->cells.erase(drv_cell); } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) { IdString drv_cell = ni->driver.cell->name; - set_net_constant(ctx, ni, vcc_net, true); + set_net_constant(ctx, ni, vcc_net.get(), true); dead_nets.push_back(net.first); ctx->cells.erase(drv_cell); } } if (gnd_used) { - ctx->cells[gnd_cell->name] = gnd_cell; - ctx->nets[gnd_net->name] = gnd_net; - } else { - delete gnd_net; - delete gnd_cell; + ctx->cells[gnd_cell->name] = std::move(gnd_cell); + ctx->nets[gnd_net->name] = std::move(gnd_net); } // Vcc cell always inserted for now, as it may be needed during carry legalisation (TODO: trim later if actually // never used?) - ctx->cells[vcc_cell->name] = vcc_cell; - ctx->nets[vcc_net->name] = vcc_net; + ctx->cells[vcc_cell->name] = std::move(vcc_cell); + ctx->nets[vcc_net->name] = std::move(vcc_net); for (auto dn : dead_nets) { ctx->nets.erase(dn); @@ -303,7 +300,7 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell) static void pack_io(Context *ctx) { std::unordered_set<IdString> packed_cells; - std::vector<CellInfo *> new_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; log_info("Packing IOs..\n"); @@ -329,9 +326,10 @@ static void pack_io(Context *ctx) } } else { // Create a SB_IO buffer - sb = create_ice_cell(ctx, ctx->id("SB_IO"), ci->name.str(ctx) + "$sb_io"); - nxio_to_sb(ctx, ci, sb); - new_cells.push_back(sb); + std::unique_ptr<CellInfo> ice_cell = create_ice_cell(ctx, ctx->id("SB_IO"), ci->name.str(ctx) + "$sb_io"); + nxio_to_sb(ctx, ci, ice_cell.get()); + new_cells.push_back(std::move(ice_cell)); + sb = new_cells.back().get(); } packed_cells.insert(ci->name); std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin())); @@ -340,40 +338,40 @@ static void pack_io(Context *ctx) for (auto pcell : packed_cells) { ctx->cells.erase(pcell); } - for (auto ncell : new_cells) { - ctx->cells[ncell->name] = ncell; + for (auto& ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); } } static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen) { std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk")); - CellInfo *gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name); + std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name); gb->ports[ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER")].net = net; PortRef pr; - pr.cell = gb; + pr.cell = gb.get(); pr.port = ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER"); net->users.push_back(pr); - pr.cell = gb; + pr.cell = gb.get(); pr.port = ctx->id("GLOBAL_BUFFER_OUTPUT"); - NetInfo *glbnet = new NetInfo(); + std::unique_ptr<NetInfo> glbnet = std::unique_ptr<NetInfo>(new NetInfo()); glbnet->name = ctx->id(glb_name); - glbnet->driver = pr; - ctx->nets[glbnet->name] = glbnet; - gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet; + glbnet->driver = pr; + gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet.get(); std::vector<PortRef> keep_users; for (auto user : net->users) { if (is_clock_port(ctx, user) || (is_reset && is_reset_port(ctx, user)) || (is_cen && is_enable_port(ctx, user))) { - user.cell->ports[user.port].net = glbnet; + user.cell->ports[user.port].net = glbnet.get(); glbnet->users.push_back(user); } else { keep_users.push_back(user); } } net->users = keep_users; - ctx->cells[gb->name] = gb; + ctx->nets[glbnet->name] = std::move(glbnet); + ctx->cells[gb->name] = std::move(gb); } // Simple global promoter (clock only) @@ -401,8 +399,8 @@ static void promote_globals(Context *ctx) } int prom_globals = 0, prom_resets = 0, prom_cens = 0; int gbs_available = 8; - for (auto cell : ctx->cells) - if (is_gbuf(ctx, cell.second)) + for (auto& cell : ctx->cells) + if (is_gbuf(ctx, cell.second.get())) --gbs_available; while (prom_globals < gbs_available) { auto global_clock = std::max_element(clock_count.begin(), clock_count.end(), @@ -419,7 +417,7 @@ static void promote_globals(Context *ctx) return a.second < b.second; }); if (global_reset->second > global_clock->second && prom_resets < 4) { - NetInfo *rstnet = ctx->nets[global_reset->first]; + NetInfo *rstnet = ctx->nets[global_reset->first].get(); insert_global(ctx, rstnet, true, false); ++prom_globals; ++prom_resets; @@ -427,7 +425,7 @@ static void promote_globals(Context *ctx) reset_count.erase(rstnet->name); cen_count.erase(rstnet->name); } else if (global_cen->second > global_clock->second && prom_cens < 4) { - NetInfo *cennet = ctx->nets[global_cen->first]; + NetInfo *cennet = ctx->nets[global_cen->first].get(); insert_global(ctx, cennet, false, true); ++prom_globals; ++prom_cens; @@ -435,7 +433,7 @@ static void promote_globals(Context *ctx) reset_count.erase(cennet->name); cen_count.erase(cennet->name); } else if (global_clock->second != 0) { - NetInfo *clknet = ctx->nets[global_clock->first]; + NetInfo *clknet = ctx->nets[global_clock->first].get(); insert_global(ctx, clknet, false, false); ++prom_globals; clock_count.erase(clknet->name); @@ -453,29 +451,29 @@ static void pack_intosc(Context *ctx) log_info("Packing oscillators..\n"); std::unordered_set<IdString> packed_cells; - std::vector<CellInfo *> new_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_sb_lfosc(ctx, ci)) { - CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"), ci->name.str(ctx) + "_OSC"); - packed_cells.insert(ci->name); - new_cells.push_back(packed); - replace_port(ci, ctx->id("CLKLFEN"), packed, ctx->id("CLKLFEN")); - replace_port(ci, ctx->id("CLKLFPU"), packed, ctx->id("CLKLFPU")); + std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"), ci->name.str(ctx) + "_OSC"); + packed_cells.insert(ci->name); + replace_port(ci, ctx->id("CLKLFEN"), packed.get(), ctx->id("CLKLFEN")); + replace_port(ci, ctx->id("CLKLFPU"), packed.get(), ctx->id("CLKLFPU")); if (bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))) { - replace_port(ci, ctx->id("CLKLF"), packed, ctx->id("CLKLF_FABRIC")); + replace_port(ci, ctx->id("CLKLF"), packed.get(), ctx->id("CLKLF_FABRIC")); } else { - replace_port(ci, ctx->id("CLKLF"), packed, ctx->id("CLKLF")); + replace_port(ci, ctx->id("CLKLF"), packed.get(), ctx->id("CLKLF")); } + new_cells.push_back(std::move(packed)); } } for (auto pcell : packed_cells) { ctx->cells.erase(pcell); } - for (auto ncell : new_cells) { - ctx->cells[ncell->name] = ncell; + for (auto& ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); } } |