Merge branch 'ice40-xy'

4 files changed, 131 insertions, 19 deletions

diff --git a/ice40/chip.cc b/ice40/chip.cc
index 05dbe7e8..b349cf12 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -364,23 +364,64 @@ PipId Chip::getPipByName(IdString name) const
 
 void Chip::getBelPosition(BelId bel, float &x, float &y) const
 {
-	// FIXME
+	assert(!bel.nil());
+	x = chip_info.bel_data[bel.index].x;
+	y = chip_info.bel_data[bel.index].y;
 }
 
 void Chip::getWirePosition(WireId wire, float &x, float &y) const
 {
-	// FIXME
+	assert(!wire.nil());
+	x = chip_info.wire_data[wire.index].x;
+	y = chip_info.wire_data[wire.index].y;
 }
 
-void Chip::getPipPosition(WireId wire, float &x, float &y) const
+void Chip::getPipPosition(PipId pip, float &x, float &y) const
 {
-	// FIXME
+	assert(!pip.nil());
+	x = chip_info.pip_data[pip.index].x;
+	y = chip_info.pip_data[pip.index].y;
 }
 
 vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
 {
 	vector<GraphicElement> ret;
-	// FIXME
+
+	auto bel_type = getBelType(bel);
+
+	if (bel_type == TYPE_ICESTORM_LC) {
+		GraphicElement el;
+		el.type = GraphicElement::G_BOX;
+		el.x1 = chip_info.bel_data[bel.index].x + 0.1;
+		el.x2 = chip_info.bel_data[bel.index].x + 0.9;
+		el.y1 = chip_info.bel_data[bel.index].y + 0.10 + (chip_info.bel_data[bel.index].z) * (0.8/8);
+		el.y2 = chip_info.bel_data[bel.index].y + 0.18 + (chip_info.bel_data[bel.index].z) * (0.8/8);
+		el.z = 0;
+		ret.push_back(el);
+	}
+
+	if (bel_type == TYPE_SB_IO) {
+		GraphicElement el;
+		el.type = GraphicElement::G_BOX;
+		el.x1 = chip_info.bel_data[bel.index].x + 0.1;
+		el.x2 = chip_info.bel_data[bel.index].x + 0.9;
+		el.y1 = chip_info.bel_data[bel.index].y + 0.10 + (chip_info.bel_data[bel.index].z) * (0.8/2);
+		el.y2 = chip_info.bel_data[bel.index].y + 0.40 + (chip_info.bel_data[bel.index].z) * (0.8/2);
+		el.z = 0;
+		ret.push_back(el);
+	}
+
+	if (bel_type == TYPE_ICESTORM_RAM) {
+		GraphicElement el;
+		el.type = GraphicElement::G_BOX;
+		el.x1 = chip_info.bel_data[bel.index].x + 0.1;
+		el.x2 = chip_info.bel_data[bel.index].x + 0.9;
+		el.y1 = chip_info.bel_data[bel.index].y + 0.1;
+		el.y2 = chip_info.bel_data[bel.index].y + 1.9;
+		el.z = 0;
+		ret.push_back(el);
+	}
+
 	return ret;
 }
 
@@ -401,6 +442,17 @@ vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
 vector<GraphicElement> Chip::getFrameGraphics() const
 {
 	vector<GraphicElement> ret;
-	// FIXME
+
+	for (int x = 0; x <= chip_info.width; x++)
+	for (int y = 0; y <= chip_info.height; y++)
+	{
+		GraphicElement el;
+		el.type = GraphicElement::G_LINE;
+		el.x1 = x - 0.05, el.x2 = x + 0.05, el.y1 = y, el.y2 = y, el.z = 0;
+		ret.push_back(el);
+		el.x1 = x, el.x2 = x, el.y1 = y - 0.05, el.y2 = y + 0.05, el.z = 0;
+		ret.push_back(el);
+	}
+
 	return ret;
 }
diff --git a/ice40/chip.h b/ice40/chip.h
index 1f46ccd2..2f0a1284 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -164,6 +164,7 @@ struct BelInfoPOD
 {
 	const char *name;
 	BelType type;
+	int8_t x, y, z;
 };
 
 struct BelPortPOD
@@ -176,6 +177,7 @@ struct PipInfoPOD
 {
 	int32_t src, dst;
 	float delay;
+	int8_t x, y;
 };
 
 struct WireInfoPOD
@@ -187,10 +189,13 @@ struct WireInfoPOD
 	int num_bels_downhill;
 	BelPortPOD bel_uphill;
 	BelPortPOD *bels_downhill;
+
+	float x, y;
 };
 
 struct ChipInfoPOD
 {
+	int width, height;
 	int num_bels, num_wires, num_pips;
 	BelInfoPOD *bel_data;
 	WireInfoPOD *wire_data;
@@ -605,7 +610,7 @@ struct Chip
 
 	void getBelPosition(BelId bel, float &x, float &y) const;
 	void getWirePosition(WireId wire, float &x, float &y) const;
-	void getPipPosition(WireId wire, float &x, float &y) const;
+	void getPipPosition(PipId pip, float &x, float &y) const;
 	vector<GraphicElement> getBelGraphics(BelId bel) const;
 	vector<GraphicElement> getWireGraphics(WireId wire) const;
 	vector<GraphicElement> getPipGraphics(PipId pip) const;
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index a106b78f..58dd0dd2 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -11,15 +11,18 @@ tiles = dict()
 
 wire_uphill = dict()
 wire_downhill = dict()
+pip_xy = dict()
 
 bel_name = list()
 bel_type = list()
+bel_pos = list()
 
 wire_uphill_belport = dict()
 wire_downhill_belports = dict()
 
 wire_names = dict()
 wire_names_r = dict()
+wire_xy = dict()
 
 def cmp_wire_names(newname, oldname):
     return newname < oldname
@@ -45,11 +48,11 @@ with open(sys.argv[1], "r") as f:
             continue
 
         if line[0] == ".buffer":
-            mode = ("buffer", int(line[3]))
+            mode = ("buffer", int(line[3]), int(line[1]), int(line[2]))
             continue
 
         if line[0] == ".routing":
-            mode = ("routing", int(line[3]))
+            mode = ("routing", int(line[3]), int(line[1]), int(line[2]))
             continue
 
         if line[0] == ".io_tile":
@@ -81,6 +84,9 @@ with open(sys.argv[1], "r") as f:
             wire_names[wname] = mode[1]
             if (mode[1] not in wire_names_r) or cmp_wire_names(wname, wire_names_r[mode[1]]):
                 wire_names_r[mode[1]] = wname
+            if mode[1] not in wire_xy:
+                wire_xy[mode[1]] = list()
+            wire_xy[mode[1]].append((int(line[0]), int(line[1])))
             continue
 
         if mode[0] == "buffer":
@@ -92,6 +98,7 @@ with open(sys.argv[1], "r") as f:
                 wire_uphill[wire_b] = set()
             wire_downhill[wire_a].add(wire_b)
             wire_uphill[wire_b].add(wire_a)
+            pip_xy[(wire_a, wire_b)] = (mode[2], mode[3])
             continue
 
         if mode[0] == "routing":
@@ -104,6 +111,7 @@ with open(sys.argv[1], "r") as f:
                 wire_uphill[wire_b] = set()
             wire_downhill[wire_a].add(wire_b)
             wire_uphill[wire_b].add(wire_a)
+            pip_xy[(wire_a, wire_b)] = (mode[2], mode[3])
 
             if wire_b not in wire_downhill:
                 wire_downhill[wire_b] = set()
@@ -111,6 +119,7 @@ with open(sys.argv[1], "r") as f:
                 wire_uphill[wire_a] = set()
             wire_downhill[wire_b].add(wire_a)
             wire_uphill[wire_a].add(wire_b)
+            pip_xy[(wire_b, wire_a)] = (mode[2], mode[3])
             continue
 
 def add_bel_input(bel, wire, port):
@@ -126,6 +135,7 @@ def add_bel_lc(x, y, z):
     bel = len(bel_name)
     bel_name.append("%d_%d_lc%d" % (x, y, z))
     bel_type.append("ICESTORM_LC")
+    bel_pos.append((x, y, z))
 
     wire_cen = wire_names[(x, y, "lutff_global/cen")]
     wire_clk = wire_names[(x, y, "lutff_global/clk")]
@@ -164,6 +174,7 @@ def add_bel_io(x, y, z):
     bel = len(bel_name)
     bel_name.append("%d_%d_lc%d" % (x, y, z))
     bel_type.append("SB_IO")
+    bel_pos.append((x, y, z))
 
     wire_cen   = wire_names[(x, y, "io_global/cen")]
     wire_iclk  = wire_names[(x, y, "io_global/inclk")]
@@ -192,6 +203,7 @@ def add_bel_ram(x, y):
     bel = len(bel_name)
     bel_name.append("%d_%d_ram" % (x, y))
     bel_type.append("ICESTORM_RAM")
+    bel_pos.append((x, y, 0))
 
     if (x, y, "ram/WE") in wire_names:
         # iCE40 1K-style memories
@@ -231,7 +243,9 @@ print('#include "chip.h"')
 
 print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
 for bel in range(len(bel_name)):
-    print("  {\"%s\", TYPE_%s}%s" % (bel_name[bel], bel_type[bel], "," if bel+1 < len(bel_name) else ""))
+    print("  {\"%s\", TYPE_%s, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel],
+            bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2],
+            "," if bel+1 < len(bel_name) else ""))
 print("};")
 
 wireinfo = list()
@@ -244,7 +258,7 @@ for wire in range(num_wires):
         for src in wire_uphill[wire]:
             if (src, wire) not in pipcache:
                 pipcache[(src, wire)] = len(pipinfo)
-                pipinfo.append("  {%d, %d, 1.0}" % (src, wire))
+                pipinfo.append("  {%d, %d, 1.0, %d, %d}" % (src, wire, pip_xy[(src, wire)][0], pip_xy[(src, wire)][1]))
             pips.append("%d" % pipcache[(src, wire)])
         num_uphill = len(pips)
         list_uphill = "wire%d_uppips" % wire
@@ -258,7 +272,7 @@ for wire in range(num_wires):
         for dst in wire_downhill[wire]:
             if (wire, dst) not in pipcache:
                 pipcache[(wire, dst)] = len(pipinfo)
-                pipinfo.append("  {%d, %d, 1.0}" % (wire, dst))
+                pipinfo.append("  {%d, %d, 1.0, %d, %d}" % (wire, dst, pip_xy[(wire, dst)][0], pip_xy[(wire, dst)][1]))
             pips.append("%d" % pipcache[(wire, dst)])
         num_downhill = len(pips)
         list_downhill = "wire%d_downpips" % wire
@@ -284,8 +298,17 @@ for wire in range(num_wires):
     else:
         info += "{-1, PIN_NIL}, "
 
-    info += ("wire%d_downbels" % wire) if num_bels_downhill > 0 else "nullptr"
-    info += "}"
+    info += ("wire%d_downbels, " % wire) if num_bels_downhill > 0 else "nullptr, "
+
+    avg_x, avg_y = 0, 0
+    if wire in wire_xy:
+        for x, y in wire_xy[wire]:
+            avg_x += x
+            avg_y += y
+        avg_x /= len(wire_xy[wire])
+        avg_y /= len(wire_xy[wire])
+
+    info += "%f, %f}" % (avg_x, avg_y)
 
     wireinfo.append(info)
 
@@ -298,6 +321,6 @@ print(",\n".join(pipinfo))
 print("};")
 
 print("ChipInfoPOD chip_info_%s = {" % dev_name)
-print("  %d, %d, %d," % (len(bel_name), num_wires, len(pipinfo)))
+print("  %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo)))
 print("  bel_data_%s, wire_data_%s, pip_data_%s" % (dev_name, dev_name, dev_name))
 print("};")
diff --git a/ice40/main.cc b/ice40/main.cc
index afdd1a4a..a32aa2db 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -24,6 +24,22 @@
 #include <boost/program_options.hpp>
 #include "pybindings.h"
 
+void svg_dump_el(const GraphicElement &el)
+{
+	float scale = 10.0;
+	std::string style = "stroke=\"black\" stroke-width=\"0.1\" fill=\"none\"";
+
+	if (el.type == GraphicElement::G_BOX) {
+		std::cout << "<rect x=\"" << (scale*el.x1) << "\" y=\"" << (scale*el.y1) <<
+				"\" height=\"" << (scale*(el.y2-el.y1)) << "\" width=\"" << (scale*(el.x2-el.x1)) << "\" " << style << "/>\n";
+	}
+
+	if (el.type == GraphicElement::G_LINE) {
+		std::cout << "<line x1=\"" << (scale*el.x1) << "\" y1=\"" << (scale*el.y1) <<
+				"\" x2=\"" << (scale*el.x2) << "\" y2=\"" << (scale*el.y2) << "\" " << style << "/>\n";
+	}
+}
+
 int main(int argc, char *argv[])
 {
 	namespace po = boost::program_options;
@@ -34,6 +50,7 @@ int main(int argc, char *argv[])
 	options.add_options()("help,h","show help");
 	options.add_options()("test","just a check");
 	options.add_options()("gui","start gui");
+	options.add_options()("svg","dump SVG file");
 	options.add_options()("file", po::value<std::string>(), "python file to execute");
 	options.add_options()("version,v","show version");	
 
@@ -71,6 +88,11 @@ int main(int argc, char *argv[])
 		return 1;
 	}
 
+	ChipArgs chipArgs;
+	chipArgs.type = ChipArgs::LP384;
+
+	Design design(chipArgs);
+
 	if (vm.count("gui")) 
 	{
 		QApplication a(argc, argv);
@@ -82,10 +104,6 @@ int main(int argc, char *argv[])
 
 	if (vm.count("test"))
 	{
-		ChipArgs chipArgs;
-		chipArgs.type = ChipArgs::LP384;
-
-		Design design(chipArgs);
 		int bel_count = 0, wire_count = 0, pip_count = 0;
 
 		std::cout << "Checking bel names.\n";
@@ -143,6 +161,20 @@ int main(int argc, char *argv[])
 		return 0;
 	}
 
+	if (vm.count("svg"))
+	{
+		std::cout << "<svg xmlns=\"http://www.w3.org/2000/svg\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n";
+		for (auto bel : design.chip.getBels()) {
+			std::cout << "<!-- " << design.chip.getBelName(bel) << " -->\n";
+			for (auto &el : design.chip.getBelGraphics(bel))
+				svg_dump_el(el);
+		}
+		std::cout << "<!-- Frame -->\n";
+		for (auto &el : design.chip.getFrameGraphics())
+			svg_dump_el(el);
+		std::cout << "</svg>\n";
+	}
+
 	if (vm.count("file")) 
 	{
 		std::string filename = vm["file"].as<std::string>();