Replace DelayInfo with DelayPair/DelayQuad

This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>

4 files changed, 42 insertions, 72 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 5b59fea4..080d6a03 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -921,7 +921,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
 
 // -----------------------------------------------------------------------
 
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 {
     if (cell->type == id_ICESTORM_LC && cell->lcInfo.dffEnable) {
         if (toPort == id_O)
@@ -932,16 +932,16 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
     return get_cell_delay_internal(cell, fromPort, toPort, delay);
 }
 
-bool Arch::get_cell_delay_internal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+bool Arch::get_cell_delay_internal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 {
     for (auto &tc : chip_info->cell_timing) {
         if (tc.type == cell->type.index) {
             for (auto &path : tc.path_delays) {
                 if (path.from_port == fromPort.index && path.to_port == toPort.index) {
                     if (fast_part)
-                        delay.delay = path.fast_delay;
+                        delay = DelayQuad(path.fast_delay);
                     else
-                        delay.delay = path.slow_delay;
+                        delay = DelayQuad(path.slow_delay);
                     return true;
                 }
             }
@@ -1088,22 +1088,22 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             NPNR_ASSERT(has_clktoq);
         } else {
             if (port == id_I0 || port == id_I1 || port == id_I2 || port == id_I3) {
-                DelayInfo dlut;
+                DelayQuad dlut;
                 bool has_ld = get_cell_delay_internal(cell, port, id_O, dlut);
                 NPNR_ASSERT(has_ld);
                 if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP4K || args.type == ArchArgs::LP8K ||
                     args.type == ArchArgs::LP384) {
-                    info.setup.delay = 30 + dlut.delay;
+                    info.setup = DelayPair(30 + dlut.maxDelay());
                 } else if (args.type == ArchArgs::UP3K || args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K ||
                            args.type == ArchArgs::U1K || args.type == ArchArgs::U2K) { // XXX verify u4k
-                    info.setup.delay = dlut.delay - 50;
+                    info.setup = DelayPair(dlut.maxDelay() - 50);
                 } else {
-                    info.setup.delay = 20 + dlut.delay;
+                    info.setup = DelayPair(20 + dlut.maxDelay());
                 }
             } else {
-                info.setup.delay = 100;
+                info.setup = DelayPair(100);
             }
-            info.hold.delay = 0;
+            info.hold = DelayPair(0);
         }
     } else if (cell->type == id_ICESTORM_RAM) {
         if (port.str(this)[0] == 'R') {
@@ -1117,8 +1117,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             bool has_clktoq = get_cell_delay_internal(cell, info.clock_port, port, info.clockToQ);
             NPNR_ASSERT(has_clktoq);
         } else {
-            info.setup.delay = 100;
-            info.hold.delay = 0;
+            info.setup = DelayPair(100);
+            info.hold = DelayPair(0);
         }
     } else if (cell->type == id_SB_IO) {
         delay_t io_setup = 80, io_clktoq = 140;
@@ -1133,26 +1133,26 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         if (port == id_CLOCK_ENABLE) {
             info.clock_port = (index == 1) ? id_OUTPUT_CLK : id_INPUT_CLK;
             info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE;
-            info.setup.delay = io_setup;
-            info.hold.delay = 0;
+            info.setup = DelayPair(io_setup);
+            info.hold = DelayPair(0);
         } else if (port == id_D_OUT_0 || port == id_OUTPUT_ENABLE) {
             info.clock_port = id_OUTPUT_CLK;
             info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE;
-            info.setup.delay = io_setup;
-            info.hold.delay = 0;
+            info.setup = DelayPair(io_setup);
+            info.hold = DelayPair(0);
         } else if (port == id_D_OUT_1) {
             info.clock_port = id_OUTPUT_CLK;
             info.edge = cell->ioInfo.negtrig ? RISING_EDGE : FALLING_EDGE;
-            info.setup.delay = io_setup;
-            info.hold.delay = 0;
+            info.setup = DelayPair(io_setup);
+            info.hold = DelayPair(0);
         } else if (port == id_D_IN_0) {
             info.clock_port = id_INPUT_CLK;
             info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE;
-            info.clockToQ.delay = io_clktoq;
+            info.clockToQ = DelayQuad(io_clktoq);
         } else if (port == id_D_IN_1) {
             info.clock_port = id_INPUT_CLK;
             info.edge = cell->ioInfo.negtrig ? RISING_EDGE : FALLING_EDGE;
-            info.clockToQ.delay = io_clktoq;
+            info.clockToQ = DelayQuad(io_clktoq);
         } else {
             NPNR_ASSERT_FALSE("no clock data for IO cell port");
         }
@@ -1162,21 +1162,21 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         if (cell->ports.at(port).type == PORT_OUT) {
             bool has_clktoq = get_cell_delay_internal(cell, info.clock_port, port, info.clockToQ);
             if (!has_clktoq)
-                info.clockToQ.delay = 100;
+                info.clockToQ = DelayQuad(100);
         } else {
-            info.setup.delay = 100;
-            info.hold.delay = 0;
+            info.setup = DelayPair(100);
+            info.hold = DelayPair(0);
         }
     } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) {
         info.clock_port = this->id("SBCLKI");
         info.edge = RISING_EDGE;
         if (cell->ports.at(port).type == PORT_OUT) {
             /* Dummy number */
-            info.clockToQ.delay = 1500;
+            info.clockToQ = DelayQuad(1500);
         } else {
             /* Dummy number */
-            info.setup.delay = 1500;
-            info.hold.delay = 0;
+            info.setup = DelayPair(1500);
+            info.hold = DelayPair(0);
         }
     } else {
         NPNR_ASSERT_FALSE("unhandled cell type in getPortClockingInfo");
diff --git a/ice40/arch.h b/ice40/arch.h
index 7280d2fe..4bac3d7a 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -578,15 +578,13 @@ struct Arch : BaseArch<ArchRanges>
         return wire_to_net[wire.index];
     }
 
-    DelayInfo getWireDelay(WireId wire) const override
+    DelayQuad getWireDelay(WireId wire) const override
     {
-        DelayInfo delay;
         NPNR_ASSERT(wire != WireId());
         if (fast_part)
-            delay.delay = chip_info->wire_data[wire.index].fast_delay;
+            return DelayQuad(chip_info->wire_data[wire.index].fast_delay);
         else
-            delay.delay = chip_info->wire_data[wire.index].slow_delay;
-        return delay;
+            return DelayQuad(chip_info->wire_data[wire.index].slow_delay);
     }
 
     BelPinRange getWireBelPins(WireId wire) const override
@@ -739,15 +737,13 @@ struct Arch : BaseArch<ArchRanges>
         return wire;
     }
 
-    DelayInfo getPipDelay(PipId pip) const override
+    DelayQuad getPipDelay(PipId pip) const override
     {
-        DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
         if (fast_part)
-            delay.delay = chip_info->pip_data[pip.index].fast_delay;
+            return DelayQuad(chip_info->pip_data[pip.index].fast_delay);
         else
-            delay.delay = chip_info->pip_data[pip.index].slow_delay;
-        return delay;
+            return DelayQuad(chip_info->pip_data[pip.index].slow_delay);
     }
 
     PipRange getPipsDownhill(WireId wire) const override
@@ -788,12 +784,7 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getDelayEpsilon() const override { return 20; }
     delay_t getRipupDelayPenalty() const override { return 200; }
     float getDelayNS(delay_t v) const override { return v * 0.001; }
-    DelayInfo getDelayFromNS(float ns) const override
-    {
-        DelayInfo del;
-        del.delay = delay_t(ns * 1000);
-        return del;
-    }
+    delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
@@ -818,10 +809,10 @@ struct Arch : BaseArch<ArchRanges>
 
     // Get the delay through a cell from one port to another, returning false
     // if no path exists. This only considers combinational delays, as required by the Arch API
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override;
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
     // get_cell_delay_internal is similar to the above, but without false path checks and including clock to out delays
     // for internal arch use only
-    bool get_cell_delay_internal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
+    bool get_cell_delay_internal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const;
     // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
     TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
     // Get the TimingClockingInfo of a port
diff --git a/ice40/archdefs.h b/ice40/archdefs.h
index 33227c6c..5caa420a 100644
--- a/ice40/archdefs.h
+++ b/ice40/archdefs.h
@@ -25,27 +25,6 @@ NEXTPNR_NAMESPACE_BEGIN
 
 typedef int delay_t;
 
-struct DelayInfo
-{
-    delay_t delay = 0;
-
-    delay_t minRaiseDelay() const { return delay; }
-    delay_t maxRaiseDelay() const { return delay; }
-
-    delay_t minFallDelay() const { return delay; }
-    delay_t maxFallDelay() const { return delay; }
-
-    delay_t minDelay() const { return delay; }
-    delay_t maxDelay() const { return delay; }
-
-    DelayInfo operator+(const DelayInfo &other) const
-    {
-        DelayInfo ret;
-        ret.delay = this->delay + other.delay;
-        return ret;
-    }
-};
-
 // -----------------------------------------------------------------------
 
 // https://bugreports.qt.io/browse/QTBUG-80789
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 18bc90aa..51138a22 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -1085,17 +1085,17 @@ void set_period(Context *ctx, CellInfo *ci, IdString port, delay_t period)
     if (to == nullptr)
         return;
     if (to->clkconstr != nullptr) {
-        if (!equals_epsilon(to->clkconstr->period.delay, period))
+        if (!equals_epsilon(to->clkconstr->period.maxDelay(), period))
             log_warning("    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
                         "%.1f MHz.\n",
-                        MHz(ctx, to->clkconstr->period.delay), to->name.c_str(ctx), MHz(ctx, period));
+                        MHz(ctx, to->clkconstr->period.maxDelay()), to->name.c_str(ctx), MHz(ctx, period));
         return;
     }
     to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-    to->clkconstr->low.delay = period / 2;
-    to->clkconstr->high.delay = period / 2;
-    to->clkconstr->period.delay = period;
-    log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(ctx, to->clkconstr->period.delay),
+    to->clkconstr->low = DelayPair(period / 2);
+    to->clkconstr->high = DelayPair(period / 2);
+    to->clkconstr->period = DelayPair(period);
+    log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(ctx, to->clkconstr->period.maxDelay()),
              to->name.c_str(ctx));
 };
 bool get_period(Context *ctx, CellInfo *ci, IdString port, delay_t &period)
@@ -1105,7 +1105,7 @@ bool get_period(Context *ctx, CellInfo *ci, IdString port, delay_t &period)
     NetInfo *from = ci->ports.at(port).net;
     if (from == nullptr || from->clkconstr == nullptr)
         return false;
-    period = from->clkconstr->period.delay;
+    period = from->clkconstr->period.maxDelay();
     return true;
 };