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authorClifford Wolf <clifford@clifford.at>2018-08-04 13:33:24 +0200
committerClifford Wolf <clifford@clifford.at>2018-08-04 13:33:24 +0200
commit700e68746ae5cf4d9b7761c4bfa515e4af5fb2b4 (patch)
tree6ad1f0e50dce4c9edaf5e2f1ad5640eaeb83633c /ice40
parentaf74f6e51136394d60384f736718056aaf422060 (diff)
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Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40')
-rw-r--r--ice40/chipdb.py10
1 files changed, 7 insertions, 3 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index c1819481..7c60a336 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -1032,16 +1032,20 @@ for wire in range(num_wires):
info["num_bel_pins"] = num_bel_pins
info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
- avg_x, avg_y = 0, 0
if wire in wire_xy:
+ avg_x, avg_y = 0, 0
+
for x, y in wire_xy[wire]:
avg_x += x
avg_y += y
avg_x /= len(wire_xy[wire])
avg_y /= len(wire_xy[wire])
- info["x"] = int(round(avg_x))
- info["y"] = int(round(avg_y))
+ info["x"] = int(round(avg_x))
+ info["y"] = int(round(avg_y))
+ else:
+ info["x"] = wire_names_r[wire][0]
+ info["y"] = wire_names_r[wire][1]
wireinfo.append(info)