ice40: General fixes

Signed-off-by: David Shah <davey1576@gmail.com>

2 files changed, 21 insertions, 11 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index dbc8036c..206811e6 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -21,6 +21,16 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+static const NetInfo *
+get_net_or_nullptr(const CellInfo *cell, const IdString port)
+{
+    auto found = cell->ports.find(port);
+    if (found != cell->ports.end())
+        return found->second.net;
+    else
+        return nullptr;
+};
+
 static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
 {
     bool dffs_exist = false, dffs_neg = false;
@@ -31,9 +41,9 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
         if (std::stoi(cell->params.at("DFF_ENABLE"))) {
             if (!dffs_exist) {
                 dffs_exist = true;
-                cen = cell->ports.at("CEN").net;
-                clk = cell->ports.at("CLK").net;
-                sr = cell->ports.at("SR").net;
+                cen = get_net_or_nullptr(cell, "CEN");
+                clk = get_net_or_nullptr(cell, "CLK");
+                sr = get_net_or_nullptr(cell, "SR");
 
                 locals.insert(cen);
                 locals.insert(clk);
@@ -43,21 +53,21 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
                     dffs_neg = true;
                 }
             } else {
-                if (cen != cell->ports.at("CEN").net)
+                if (cen != get_net_or_nullptr(cell, "CEN"))
                     return false;
-                if (clk == cell->ports.at("CLK").net)
+                if (clk != get_net_or_nullptr(cell, "CLK"))
                     return false;
-                if (sr != cell->ports.at("SR").net)
+                if (sr != get_net_or_nullptr(cell, "CEN"))
                     return false;
                 if (dffs_neg != bool(std::stoi(cell->params.at("NEG_CLK"))))
                     return false;
             }
         }
 
-        locals.insert(cell->ports.at("I0").net);
-        locals.insert(cell->ports.at("I1").net);
-        locals.insert(cell->ports.at("I2").net);
-        locals.insert(cell->ports.at("I3").net);
+        locals.insert(get_net_or_nullptr(cell, "I0"));
+        locals.insert(get_net_or_nullptr(cell, "I1"));
+        locals.insert(get_net_or_nullptr(cell, "I2"));
+        locals.insert(get_net_or_nullptr(cell, "I3"));
     }
 
     locals.erase(nullptr); // disconnected signals don't use local tracks
diff --git a/ice40/picorv32_arachne.sh b/ice40/picorv32_arachne.sh
index e166487a..00cfe6a4 100755
--- a/ice40/picorv32_arachne.sh
+++ b/ice40/picorv32_arachne.sh
@@ -4,6 +4,6 @@ rm -f picorv32.v
 wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
 yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v
 arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif
-yosys picorv32_place.blif -p "read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json"
+yosys -p "read_blif -wideports picorv32_place.blif; read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json"
 ./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json
 ../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32_place_nx.json