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| author | Sylvain Munaut <tnt@246tNt.com> | 2020-06-02 11:02:48 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-06-02 11:03:04 +0200 |
| commit | 5e2b6bcef945a89daa215d01e15120162f81da7b (patch) | |
| tree | 3e81b142d49c8cfde7e331f88de71043259e8c86 /ice40 | |
| parent | f44498a5301f9f516488fb748c684926be514346 (diff) | |
| download | nextpnr-5e2b6bcef945a89daa215d01e15120162f81da7b.tar.gz nextpnr-5e2b6bcef945a89daa215d01e15120162f81da7b.tar.bz2 nextpnr-5e2b6bcef945a89daa215d01e15120162f81da7b.zip | |
ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE
This requires the matching chipdb update from icestorm project !
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/bitstream.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 9586b8ff..3865316f 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -718,7 +718,7 @@ void write_asc(const Context *ctx, std::ostream &out) {"PLLOUT_SELECT_A", 2}, {"PLLOUT_SELECT_B", 2}, {"PLLTYPE", 3}, - {"SHIFTREG_DIV_MODE", 1}, + {"SHIFTREG_DIV_MODE", 2}, {"TEST_MODE", 1}}; configure_extra_cell(config, ctx, cell.second.get(), pll_params, false, std::string("PLL.")); |